"wired AND" in I2C?

[Kittu20]

I'm trying to understand I2C bus specification and stuck on a paragraph on page 8, in  3.1.1, that's left me with a question. It say :

"When the bus is free, both lines are HIGH. The output stages of devices connected to the bus must have an open-drain or open-collector to perform the wired-AND function."

Could you help clarify if the concept of a "wired AND gate" in traditional digital logic gates aligns with the "wired AND" in I2C?


Specifically, I'm wondering if it's same to connecting M1 and M2 to the SDA and SCL lines to achieve an AND behavior, similar to the truth table

M1 | M2 | SDA
 0    0    0
 0    1    0
 1    0    0
 1    1    1


M1 and M2 refer as two master devices and SDA are output line

[ataradov]

Yes, it is exactly the same thing. I2C pull-up resistors ensure high level, any or multiple of the transistors driving the line low will result in a low level.

[HwAoRrDk]

Yes, it's the same. Your truth table applies to the behaviour of nodes in the bus.

If you think of a node driving a bus line low as a '0', and a node not driving a line as a '1', then you can consider the truth table to be as follows:

M1	M2	SDA/SCL	Bus State
0	0	0	Both nodes are driving the bus low, so bus is low (but in reality this won't happen due to arbitration)
0	1	0	M1 is driving the bus low, M2 is doing nothing, resulting in bus low
1	0	0	M2 is driving the bus low, M1 is doing nothing, resulting in bus low
1	1	1	Neither node is doing anything, so bus idles high (due to pull-ups)

[Kittu20]

I have a question regarding the operation of the I2C bus, particularly in scenarios where multiple masters attempt to take control simultaneously.

As I understand it, when multiple masters initiate a start condition to pull SDA line low, one of them successfully gains control of the bus while others detect that someone has taken to control of I2C bus by monitoring the SDA line.

How the masters monitor or read the SDA line to determine that someone else has taken control of the bus. ?

When does other monitor SDA line? When does it happens before start conditions, after stop condition or during start conditions?

[ejeffrey]

It's continuous.  Because of the wired-and behavior, it's not possible to tell if two devices are simultaneously pulling SDA low as the result is the same.  Instead, during the master write phase, the master needs to send a series of high and low bits.  If it ever detects that it is trying to send high but the line is low, it determines another master is transmitting and cancels it's transmission. 

[ataradov]

What do you mean by "how"? The only way to monitor the state of the line is by reading the voltage level on the corresponding pin.

This monitoring happens for all bits (SCL edge transitions). Master always knows what level it wants to drive and always knows what level is actually present on the bus. If they do not match, then there is a conflict.

There is no special "monitoring", it is just an ongoing comparison of the desired level and the actual level. Once they do not match, a bus collision is indicated.

[HwAoRrDk]

If you mean by "how", how can the master read the voltage level on the SDA pin and also use it as an output, don't forget that on most (all?) microcontrollers, when a pin is set as an output (whether that be push-pull or open-drain) the input circuitry is not actually disabled, so you can still read the state of the pin. You'd normally just be reading back whatever state you last put the output in. But in the case of I2C, where the MCU pins will be configured as open-drain outputs, other devices on the bus can independently affect the state of the line, so the output state might be commanding 'high' but the pin input actually reads 'low'.