Btw. I still believe the the analog watchdog pushed to extreme (6-bit conversion, shortest possible sampling - this is subject to experimentation due to PA7 being "slow" ADC input), triggering TIM1 through ETR_ADC1_RMP, is a viable option; of course depending on whether your application uses ADC1 in any other way or not.
Latency is IMO comparable to EXTI - if 2.5tADC sampling time would be viable, a conversion is 9cyc but even with 6.5tADC sampling it's just 13cyc; plus whatever time it takes the ADC to perform the WD comparison and propagate the signal to TIM, but that IMO should be well below half a dozen, so that's say 15-20cyc. Unfortunately 9/13cyc of that is jitter, too.
Conversely with EXTI, considering minimal hand-optimized-in-asm ISR running out of 0WS memory (RAM), latency is 12+longest_instruction+load_TIM_address+load_value_to_trigger_TIM+store_to_TIM, and that would be 15-20cyc :-). However, this assumes EXTI being of highest priority, and that there is no interrupt disable in the code. This is probably easier to write than the ADC_WD solution and allows any TIM to use, and the jitter will be lower, too; OTOH this is software with all the consequences.
JW