STM32L4P5 OctoSPI (and quadSPI) peripheral behaviour in SingleSPI mode

[ogoun]

Hi all,

I am trying to understand how the OctoSPI and QuadSPI peripherals work in single-spi mode, specifically as to how they treat the IO2/nWP line.

When the attached spi device (in my case, a NOR flash memory) operates in singlespi mode, i.e. after reset or power cycle, the line used for IO2 becomes nWP (active LOW write protect input to the memory chip).

According to the reference manual (sect 19.4.4 of RM0432) and AN4760:

Single-SPI mode (from RM0432):

The legacy SPI mode allows just a single bit to be sent/received serially. In this mode, the
data is sent to the external device over the SO signal (whose I/Os are shared with IO0). The
data received from the external device arrives via SI (whose I/Os are shared with IO1).
The different phases can each be configured separately to use this Single-bit mode by
setting to 001 the IMODE, ADMODE, ABMODE, and DMODE fields in OCTOSPI_CCR and
OCTOSPI_WCCR.
In each phase configured in Single-SPI mode:
• IO0 (SO) is in output mode.
• IO1 (SI) is in input mode (high impedance).
• IO2 is in output mode and forced to 0 (to deactivate the “write protect” function).
• IO3 is in output mode and forced to 1 (to deactivate the “hold” function).
• IO4 to IO7 are in output mode and forced to 0.
This is the case even for the dummy phase if DMODE[2:0] = 001.

 My first read of this was WTH?? Low Activates the WP function, it doesn't deactivate it!

Write protect on all spi/qspi/octospi nor flash chips I have looked at is active low.

The diagram in AN4760 even shows the wp input on the attached memory device as active low (nWP), while simultaneously saying that low deactivates the memory device's write protect!

So, as I read this, the default operating mode of the QuadSPI and OctoSPI STM32 Peripherals, when set to operate in Single-SPI mode, is that it will drive the memory device's IO2 (now repurposed as nWP) pin LOW, thus ENABLING the chip's Write Protect function!

This can cause all kinds of grief, as the IO2 signal does not appear to be alterable, and in some cases, quad or octo mode cannot be entered when WP is active! This can happen on the Macronix MX25L25645G part, and several others as well. All it takes is for the status register SRWD bit to be set, and then the memory device is stuck in singlespi mode, and effectively read only, possibly "bricking" the product.

Can anyone confirm if the IO2 signal does actually operate in this way?

If it does indeed operate in this way, I am thinking that while in singlespi mode, I might have to override the IO2 signal by reconfiguring it as a gpio output, and set it high. Then, when entering quad or octo mode, releasing the gpio pin back to the quad or octo spi peripheral's alternate function (as IO2)..

Very interested in what others have found with this (I am hoping it is a typo, and not real behaviour).


Cheers,

Pete

[woofy]

AFAIK, the octal MX25L25645G used on STM's boards does not have a WP pin.

[ogoun]

Hi woofy,

25LM25645G is ospi (this is the one on the STM boards), the 25L25645G is qspi.

Cheers,
Pete