Electronics > Microcontrollers

STM32U3 announced

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hans:
I've looked at Ambiq micro's before, but their peripheral system is extremely simple and limiting. The CPU runs very efficient, but for applications that need to wait on I/O (or handle I/O without much CPU activity) it didn't look great at all.
But that was over 2 years ago when I last looked.

I really like the U5 series (and Silabs MCUs) because of their I/O subsystem flexibility. Unfortunately, the STM32U0 was heavily trimmed down on that, and afaik didn't contain the LPBAM peripheral subdomain.  It has some limitations on the STM32U5, including needing a bit more explicit documentation, but it was really nice to have everything happening in hardware and only wake the main CPU e.g. once every 64 samples transferred.

The remaining downside for my application was the high oscillator start-up currents. The firmware was doing wakeups at 8kHz, and even if an oscillator only takes 10nAs to start up thats still 80uA right there. A program running with 5% CPU time @ 24MHz would consume 58uA (for about 1.20MHz), so unfortunately that ratio is still dominated by I/O

So keen to see what ST can do on this part. I know 8kHz I/O wakeups is a lot, but IMO that's the whole point of the LPBAM so it can put the CPU to sleep as much as possible. I hope they can apply some more analog magic here, as lower oscillator overhead would really stretch the current vs I/O wakeup frequency a lot further down.
If you want to know what kind of graphs I'm talking about, see figure 11 in : https://www.st.com/resource/en/application_note/an5645-stm32u5-series-power-optimization-using-lpbam-stmicroelectronics.pdf

tszaboo:

--- Quote from: SiliconWizard on January 24, 2025, 08:42:17 am ---
--- Quote from: Whales on January 24, 2025, 06:39:16 am ---
--- Quote from: SiliconWizard on January 24, 2025, 05:09:25 am ---Yes, Ambiq has been doing this for over 10 years. https://ambiq.com/soc

I believe that what Ambiq implements is covered by a number of patents, so it'll be interesting to see how ST did it, how it is different.

--- End quote ---

The datasheet for their Apollo4 claims "5 µA/MHz active mode current" and "up to 250Mhz".  Wow, that would only be 1.25mA.  Suspiciously good, I've never heard of these things, maybe I'm misunderstanding and the power draw isn't as good as this in practice?

--- End quote ---

This is the lowest achievable figure, of course, as with all such figures announced in datasheets. But it is true - it's the active mode current of the CPU core only (no peripheral enabled, no DMA, ...) plus exec. from RAM (I think?), and probably with not all RAM banks enabled. Also, at least that was the case for the Apollo 3 and older, the lowest power consumption per MHz can be achieved only up to a certain frequency, beyond which you need to enable a "turbo" mode (probably increasing the gate voltage a bit) which draws a bit more, but still with an impressive figure. For instance, the Apollo 3 has its lowest power consumption mode up to 48 MHz, beyond which you need to enable this turbo mode (up to 96 MHz). I have a dev board of these, so I can confirm it does match the datasheet figures. Of course, in practice, with a few peripherals enabled and such, you'll get a much higher figure, but still pretty impressive

We had discussed using these chips in commercial products with a forum user, the name of which I don't remember - he seemed to say that Ambiq was not great to deal with. I haven't had any direct contact with them personally, so I can't tell.

Relatively excited to see this in a ST product, but we'll see what the specs are...

--- End quote ---
Probably creative accounting on that power consumption. I think by subthreshold, they mean that the core voltage is low, maybe 0.9V-1.2V. You measure the current consumption on the input, and DC-DC it down to the core. So 10uA/MHz on the 3.6V input, and more on the core.
Which is still good. The micros I'm using now are (silicon labs):
38.4 MHz crystal, CPU running Prime from flash: 30 µA/MHz (with DC-DC)
So this is much better. I'm not sure how much effect it has on real world battery life, this is really diminishing returns. And things like time to enter sleep mode matters more than the core consumption. Plus, you can often times just write better code.

SiliconWizard:
No, 0.9V-1.2V is the normal range for the process nodes and kind of transistors that are commonly used on MCU *cores* these days and that's what you already have in most of the reasonably recent STM32 MCUs.

Subthreshold is more commonly in the 0.5V-0.8V range on these process nodes. And there's a pretty significant difference in that transistors are not driven to saturation, which requires some clever tricks. It's not just a marketing gimmick.

Those interested in the concept can start here: https://www.sciencedirect.com/science/article/pii/S2090447916300685

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