Many old designs are rubbish, but some ideas have stood the test of time.
Most curiously, the VAX was also loosely based on the PDP-11 (orthogonal src/dst, register file, addr modes) but turned out to be rubbish. The microcoded design just couldn't be scaled, and DEC couldn't throw real estate at the problem the way Intel did a couple of decades later with the x86.
That's not what it was about.
The VAX was designed with two main goals:
1) support a flat 32 bit address space with page-based virtual memory
2) allow assembly-language programmers to write programs using fewer lines of code (fewer instructions), in the belief that the main productivity driver.
The VAX was to solve the "software crisis", in which computer hardware was getting exponentially cheaper while programmers were getting more expensive, and as computers got cheaper more sites bought them and they all needed more and more custom software.
DEC knew full well that the VAX 11/780 would be a little slower than a PDP 11/70 on software that fit on a PDP 11, but it DIDN'T MATTER because the machines were going to be so much cheaper (certainly by the time they got to the 2nd or 3rd model) so the customer could just buy several of them if necessary. And VAX code would get written so much more quickly with the more expressive instruction set and without the 64 KB memory limit.
As for Intel throwing silicon at the problem, that is true to a certain extent, but *both* PDP11 and VAX have fundamental problems that make them less able to use advanced implementation techniques than x86. Except for a couple of weird cases such as MOVSB, x86 instructions only ever have one memory operand and -- more importantly -- that operand only accesses one memory address.
VAX has up to six or so memory operands (with three being extremely common). PDP-11 only has two. But that is still much worse than one.
And even PDP-11 has addressing modes that load something from memory and then use the thing just loaded as a pointer to load or store the actual data somewhere completely different in memory.
You can split up these multiple operands and complex addressing modes into µops, but the *problem* is that a single instruction can cause four different TLB misses / page faults on the PDP-11 and dozens on the VAX, and this makes it really really hard to save pipeline state, call an OS handler to fix everything up, and return to the right part of the instruction that had the problem.
x86 only ever accesses one memory address with one instruction, making things much much simpler.
In fact x86 can get two page faults from a single instruction if the data being accessed is misaligned AND crosses a 4K page boundary. But this is both extremely rare AND something that the page fault handler can detect, and fix up both adjacent pages at the same time before returning. And just retry the whole instruction again from the start.