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Tiny MCU architectures: AVR, PIC, 8051, STM8, MSP430, custom RISC...

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josuah:
A lot of interesting approaches, and promising low-power, low-price, high-reliability (in various amount) in the 8-bit world.
I did not find a place that was comparing the architecture of these MCU, so I am collecting wisdom and trying to dive down this littlebig world and report what I found.

Note: I am not curious about which is better, just trying to understand what makes an 8-bit instruction set modern, and what is the way followed by 8-bit MCUs.

AVR is said to be a newer architecture, has a maintained GCC port (it was about to be dropped but survived!).
It has an interrupt system requiring the push all registers used by the ISR, which I think GCC can minimize as an optimization.

8051 have multiple register banks which dodge that problem by switching to a new set of registers while entering an interrupt and going back to the usual register set when leaving.
12T instructions (12 clocks ticks per CPU instruction) for everything... only for very old 8051, and 1T for most instructions for the modern 8051.

PIC uses paging for accessing RAM, instead of concatenating two registers (the "X", "Y", "Z" registers on AVR, or DPTR on 8051).
Mostly used with assembly, or a proprietary C toolchain or an endangered(?) SDCC compiler port.

MSP430, I do not know much about it, except it is a 16-bit arch which avoids some of the problems of 8-bit registers. I suppose 16-bit address space.

STM8 has interesting features such as having a single address space ("modified Harvard"?) for everything, I do not know much more.

PicoBlaze which is FPGA-Only is taking an interesting approach to use fewer LUT. https://en.wikipedia.org/wiki/PicoBlaze#Architectural_notes
But noone producing any of these on a foundry AFAIK.

Now in all of this, something I wonder: Why is AVR said to be a modern architecture than, say, 8051?

* The fact that it has 3 memory pointers? X, Y, Z vs just DPTR
* No limitation to just an accumulator register? Although does it much change anything in practice outside compiler optimization?
* The fact that it is 1T for most things? Which is also true for modren 8051
* A simpler instruction set encoding scheme? Like how RISC-V is said to be modern for having a easy to implement instruction decoding
  Although looking at AVR and 8051, I find the AVR a bit more complex and irregular
  https://en.wikipedia.org/wiki/Atmel_AVR_instruction_set#Instruction_encoding
  https://en.wikipedia.org/wiki/Intel_8051#Instruction_set
* The limited set of instructions (RISC)? Recent 8051 are hardwired rather than microcoded (C8051 from these same EFM8BB), and 128 of the 256 instructions are for specifying the register to work on.

Last but not least, any hint in what makes an 8-bit power-efficient (how to get the core smaller, spend less time doing more things to go back to sleep quicker using less power, etc...) and simple to implement (say, on an FPGA) is welcome!

Thank you! :)

Picuino:
The microcontroller core is important, but not the only thing. The peripherals matter just as much, if not more.

AVR has a superb core and a port of GCC as a compiler.

The PIC core doesn't look as good to me, but PICs have a great peripheral system.

Now that Microchip has bought Atmel, some AVRs are appearing with PIC peripherals, which in my opinion is the best combination that could be made.

rhodges:
The STM8 is my favorite 8-bit MCU. It has a nice set of addressing modes, and the SP + offset is very handy. Writing to Flash and EEPROM is super easy. The interrupt vector table makes ISRs straightforward. Programming the chips is also fast and easy with ST-LINKv2 USB adapters.

Kleinstein:
The actual CPU part of a µC is usually only a small part of the chip. So the core size is less relevant. This makes it possible the 16 bit MSP430 to compete with the 8 bit ones. often ADC and similar mesured values are more like 10-12 bit wide and thus need 2 byte operations. So the 16 bit CPU makes absolute sense and indeed saves some hassles, e.g. with 8 bit acess to 16 bit counters or 10/12 bit ADC results.
With plenty of transistors available a small CPU is less important, it is now more about relatively small code a compiler can produce.
How much power a µC uses depends a lot on the production technology used - the instruction set is more like a small part here, though it does have some effect.
As an odd side effect the chips with more transistors may consume less power as they tend to use smaller strucktures.

The AVRs are relatively new (the 8051 and PICs (e.g. PIC16) are quite old and from times when the transistors in the actual CPU mattered a bit more).
To make a GCC port easy the AVR CPU has quite a lot of similar CPU registers and avoids the RAM / register paging of the 8051 / PIC than can make programming quite a hassel.
However the separate code / RAM adress spaces also causes some hassels for the compiler / programmer.
The more RISC like commands (seprate load/store and ALU commands) also works well with the opimization of modern compilers made with Risc processors in mind. The compilers have also changed: In the early days the stack oriented TMS1000 was easy for a compiler.

AFAIK a large point to make the AVRs quite popular was also that they were relatively fast to include flash memory instead of OTP memory.
Having to save the registers by the ISR code is a common solution, it keeps the CPU simple and in most cases only some registers are needed and this part is more like easy for the compiler.

PCB.Wiz:

--- Quote from: josuah on November 15, 2022, 05:23:34 pm ---A lot of interesting approaches, and promising low-power, low-price, high-reliability (in various amount) in the 8-bit world.
I did not find a place that was comparing the architecture of these MCU, so I am collecting wisdom and trying to dive down this littlebig world and report what I found.

Note: I am not curious about which is better, just trying to understand what makes an 8-bit instruction set modern, and what is the way followed by 8-bit MCUs.

--- End quote ---

It is useful to include the opcode size range, for MCU comparisons.
eg PIC's vary with 12 and 14 and 16b opcodes, for various models, and the tiny PICs have very limited HW stacks.
8051 have 1,2,3 byte opcodes

The oldest NMOS 8051's had a 6 clock phase, and needed 12 or 24 clocks for most opcodes.
The more modern 1T 8051 started with mostly 1 clock per byte, but some recent models use a 32 bit fetch, and on those models a 24bit opcode can execute in 1 sysclk. 


You could also include parts like Zilog Z8 (8b) and Siemens (infineon) C166 (16b)   FWIR those both used a register frame pointer, which allowed register banks to be moved across RAM space.
That expanded on the 8051's 4 register banks for interrupts.


--- Quote from: josuah on November 15, 2022, 05:23:34 pm ---Last but not least, any hint in what makes an 8-bit power-efficient (how to get the core smaller, spend less time doing more things to go back to sleep quicker using less power, etc...) and simple to implement (say, on an FPGA) is welcome!

--- End quote ---

power-efficient is mostly the process.
getting the core smaller usually means getting it simpler.  eg Multiply and Divide are nice to have but costly in core area.

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