$0.11 PY32F002A: Cortex-M0+ MCU, actually a PY32F030! 32/4KB, 48MHz, PLL, DMA...

[DavidAlfa]

Try interrupt instead?

[andrvisht]

It works by interrupt.
Moreover, setting or resetting the bit

Code: [Select]

EXTI->IMR = EXTI_IMR_IM19;does not affect its behavior in any way.
And I can't understand this either... 

Since RTC has a separate vector, what does channel 19 EXTI control?
And if this is it, then why the interrupt enable bit

Code: [Select]

RTC->CRH = RTC_CRH_ALRIE;
Well, the main question is how to configure by event ...

PS:

Can someone explain how NVIC is arranged in the event area?

From the description of the core, we can conclude that there is one event input, which probably comes from the EXTI controller.
And then the 19th line of the RTC should be connected to it.
But what is this line ....
It is mentioned only in the description of EXTI, there is not a word about this line in the RTC module itself.
There are no explanations in the figure either.
But, what is interesting ... after all, WFE expects an event bit.
This bit, apparently, is set after the execution of the ISR, or in the presence of an external event.
The problem is apparently that this line either does not exist, or it is prohibited.
This means that there are some conditions under which it passes from the RTC to the kernel event line ...

For now such thoughts...

[DavidAlfa]

Try following an existing example:

https://github.com/IOsetting/py32f0-template/blob/289ffc80de237c46171635b0f03b76b1a7f765be/Examples/PY32F0xx/LL/PWR/PWR_Stop/main.c#L58

[andrvisht]

This is a good example, and I checked the operation with the button.
The point is that with GPIO everything works correctly,
but the EXTI lines for GPIO have their own handlers in NVIC.

And in the case of RTC and LPTIM, the handlers have their own dedicated addresses,
and the lines 19 and 29 themselves go to God knows where.
Since there is no handler for these channels.

And in the case of RTC and LPTIM, if their interrupts are disabled, then the events are not issued,
or do not get where they should

And since the state of bits 19 and 29 IMR does not affect the operation of the interrupt handler, I assume that it wakes up not from these channels at all, but from NVIC.

[DavidAlfa]

Have a look at the official library examples, maybe you find something useful:

https://www.puyasemi.com/download_path/%E5%BA%93%E5%87%BD%E6%95%B0%E4%B8%8E%E4%BE%8B%E7%A8%8B/MCU%20%E5%BE%AE%E5%A4%84%E7%90%86%E5%99%A8/PY32F002B_Firmware_V1.1.4.rar

[andrvisht]

Yeah, thanks.
I have a similar selection, but earlier versions.
At the moment I managed to get the RTC to react to the event, but for this I need to disable the interrupt itself in NVIC.
Probably the signal which according to the manual is called direct connection is an interrupt signal.
As for IMR, these bits still do nothing.
In addition, the role of the SAVEOPEND bit in the kernel is still unclear.
I continue to investigate.

[DavidAlfa]

I'd check the ARM M0+ core docs, that part is almost never described in RMs or datasheets.

[andrvisht]

results of my experiments.
In order for channels 29 and 19 to be connected to EXTI, you need to set the interrupt enable bits for these modules.
Then, the enable is controlled by EMR and IMR.
regarding SEVONPEND:
setting it will allow waking up even from disabled interrupts of NVIC channels, provided that WFE is used.
In this case, you need to monitor the reset of the flags of these channels manually NVIC_ClearPendingIRQ(), since only the transition from 0 to 1 of this bit initiates the wake-up event.
The functionality itself is rather questionable, it would be easier to configure it by event, but ... as it is.
Thanks for your help.