Author Topic: Transport Triggered Architecture Toolset: TCE  (Read 1032 times)

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Offline obiwanjacobi

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Transport Triggered Architecture Toolset: TCE
« on: January 30, 2018, 05:21:09 pm »
Anyone ever played with this?
https://tce.cs.tut.fi/index.html

I was looking into what it would take to write a compiler for a TTA CPU architecture and found this.
Have not fully wrapped my head around it, but it doesn't look half bad.

 :popcorn:
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Offline obiwanjacobi

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Re: Transport Triggered Architecture Toolset: TCE
« Reply #1 on: March 02, 2018, 08:36:31 am »
I have installed it on an Ubuntu VM (I'm on Windows) and it looks really nice.
I do not have any Linux experience, so some of the simple things require me to look it up online, but I'm getting the hang of it.

Installation is described nicely (use the install.debian for Ubuntu) and everything worked as described - I only remember one occasion where I had to sudo-force it when it gave an access error.

I am now doing the tour-tutorial -about half way there (don't have much time). It seems geared towards designing custom CPU resources (Functional Units) to get better performance for a specific type of benchmark. Not really what I am after but it does allow you to get acquainted with their toolset.

It is really worth checking out if you are interested in Transport Triggered CPU Architectures.
[2c]
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Offline hans

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Re: Transport Triggered Architecture Toolset: TCE
« Reply #2 on: March 02, 2018, 12:38:47 pm »
It seems geared towards designing custom CPU resources (Functional Units) to get better performance for a specific type of benchmark. Not really what I am after but it does allow you to get acquainted with their toolset.

ASIPs, which TTA is targeting, are used to accelerate certain algorithms in a custom processing application really well, while maintaining programmability/flexibility of a normal CPU. If you read up on ASIPs you will see these kind of systems bridge the gap between CPU's and ASIC's.

It's somewhat similar to synthesizing a softcore processor on a FPGA, but instead of expanding a standard CPU architecture with custom peripherals and instructions, in this case describing how algorithms should map onto functional units (e.g. via a data dependency or signal-flow graph) and deriving a custom data-path (and instruction set) from that (note: I'm skipping plenty of transformation steps in this explanation). It's basically 1 level extra down from a CPU, but not so much that everything is hardwired/fixed once synthesized, which basically would turn it into an ASIC.

It seems like this solution is trying to offer microcode level granularity control of the machine, much like a VLIW machine. That is interesting, but it does put a lot of emphasis on good compiler tools as they are key in utilizing the most of the available data-path.
 

Offline obiwanjacobi

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Re: Transport Triggered Architecture Toolset: TCE
« Reply #3 on: March 02, 2018, 12:56:11 pm »
It seems geared towards designing custom CPU resources (Functional Units) to get better performance for a specific type of benchmark. Not really what I am after but it does allow you to get acquainted with their toolset.

ASIPs, which TTA is targeting, are used to accelerate certain algorithms in a custom processing application really well, while maintaining programmability/flexibility of a normal CPU. If you read up on ASIPs you will see these kind of systems bridge the gap between CPU's and ASIC's.

It's somewhat similar to synthesizing a softcore processor on a FPGA, but instead of expanding a standard CPU architecture with custom peripherals and instructions, in this case describing how algorithms should map onto functional units (e.g. via a data dependency or signal-flow graph) and deriving a custom data-path (and instruction set) from that (note: I'm skipping plenty of transformation steps in this explanation). It's basically 1 level extra down from a CPU, but not so much that everything is hardwired/fixed once synthesized, which basically would turn it into an ASIC.

Ah, yes fits perfectly with what I understand this is trying to do.

It seems like this solution is trying to offer microcode level granularity control of the machine, much like a VLIW machine. That is interesting, but it does put a lot of emphasis on good compiler tools as they are key in utilizing the most of the available data-path.

Yes, as part of the installation is compiling a customized version of LLVM that takes care of the compilation needs. The tour-tutorial I talked about earlier goes into optimizing a CRC routine (code) by adding a specialized Functional Unit. It is also easy to test a program against a CPU architecture with several different inter-connections (number of busses and the number and content of the FUs) and get simulation results on number of cycles and utilization of FUs etc.
I was really impressed when I saw that for the first time.
« Last Edit: March 02, 2018, 12:59:08 pm by obiwanjacobi »
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