Tutorial on Microprocessor/Memory Track Length ERC?

[TripleFault]

I watched a video on You tube recently, where the guy went to extreme lengths to ensure that all the tracks (Address/Data Busses) from the uC were the same length.
I guess that is to do with Bus loading/Timing Latency, due to capacitive loading etc.

What I would like to know, is there any tutorials that anybody knows of, that lay out the Bus Timing/ERC Rules etc for matching track lengths when designing uC PCBs??

Any help would be appreciated.

Cheers 

[Kremmen]

There are numerous reasons why you might wish to pay attention to the track lengths. However, that is just one of the outcomes of the underlying fundamental reason to get interested in that general topic.

In digital circuits there is a fuzzy line where the nice lumped objects turn into distributed ones and all kinds of new phenomena creep in. As far as PCBs are concerned, your nice digital pulses gradually turn into "swells" that travel to and fro in the conductors on the PCB - rather like a cross section of the surface of a restless swimming pool if you can picture that in your head.
Take the rising edge of a signal pulse. These always have 2 things associated with them: the rise time from the initial to the final state and the speed of signal propagation in the medium where the pulse travels. An example might illustrate: take a fast logic output rising from 0 to (say) 1 volt in 1 ns. On a typical outer layer track on FR4 substrate the leading edge of that signal would propagate some 180 mm before the trailing edge would leave the device output. So now the signal is distributed in the form of a rising swell over 180 mm of PCB track. To make matters worse, wherever there is a discontinuity in the track, or even a sharp bend, there will be reflections. All of those as well as the far end of the track cause reflections when/if the characteristic impedance of the track and the feature do not match. Radio amateurs are well aware of this in their pursuit of maximum energy transfer from the transmitter to the feeder cables, antenna and the ambient space. Same principles apply here, althoug in a different environment.
So, not only do you wish to match the length of the tracks (and not always to the same numerical length either), but also you will want to match the track characteristic impedance with those of the source and load, in order to avoid reflections.
If you look carefully at some commercial high speed circuits, such as can be found in computers, game consoles etc, you will see lots of tiny smd resistor arrays; these are used for bus termination / impedance matching. On a PCB the impedance matched transmission line almost always takes the form of a microstrip or stripline where well known formulas for strip dimensions exist for various configurations.

You will start to see ringing (multiple signal reflection from the trace endpoints) and overshoot after the trace length exceeds the so called round trip delay, i.e. the time the rising slope takes to travel there and back before the signal has fully risen. In the previous example that would be around 90 mm. These phenomena are simple in concept but a bit more complex to analyze mathematically. The factors impacting oversoot and ringing depend on path length but also on the input acceptance function, far end and near end reflection coefficients and the far end transmission function. In turn, all of those depend on the values of source, load and transmission line impedances.

I am not aware of any "101" or  "... for Idiots" type of tutorial on the subject. On the other hand there are numerous texts in book form covering the topic form fundamentals to painful details. You are guaranteed to find the necessary information in one of those, but not without effort on your part.
One book comes to mind that i bought some time ago, recommended by a countryman on another forum. It is an older text but quite valid, and could perhaps be found cheaply as a used book: H. Johnson, M. Graham: High-Speed Digital Design; a Handbook of Black Magic (see http://www.amazon.com/High-Speed-Digital-Design-Handbook/dp/0133957241/ref=sr_1_1?ie=UTF8&qid=1335860903&sr=8-1) Amazon unfortunately does not have cheap used versions at this time but someone might.

Edit: Altera to the rescue : http://www.altera.com/literature/an/an224.pdf

[graynomad]

Bet you're sorry you asked now TripleFault

What sort of PCB/uC do you have in mind, truth is for the average hobbiest (and even professional) PCB none of this matters, nothing is fast enough.

______
Rob

[free_electron]

It's not until you hit the 200Mhz range that stuff starts getting critical.
If you make sure you daisy chain all nets and you make the rd wr or clock line longer than then longest data/address line you are generally good.
Modern cpu's have controlled slew rates and current mode pin drivers. this already solves a lot of problems. Avoid T-stubs , avoid unneccesarey layer hopping and it will get pretty good.

Now, if you are concerned about EMC , that's another problem...

[nctnico]

I watched a video on You tube recently, where the guy went to extremem lengths to ensure that all the tracks (Address/Data Busses) from the uC were the same length.
I guess that is to do with Bus loading/Timing Latency, due to capacitive loading etc.

What I would like to know, is there any tutorials that anybody knows of, that lay out the Bus Timing/ERC Rules etc for matching track lengths when designing uC PCBs??

This usually becomes an issue when doing a layout for the memory connected to a SoC (system on chip). Most SoCs come with a manual on how to route the traces. Whether a design is very sensitive depends on the type of memory not so much on the frequency. In most cases the order of the layers is also important.

[free_electron]

It's got nothing to do with the type of memory. it's all about edge rates , meeting setup and hold times and avoiding excessive overshoot , and especially undershoot. Fail to meet the logic levels in the right amount of time and it all goes to snot.

There's two things when it comes to high speed boards : signal integrity and EMC. They are related but not the same. to get your system working signal integrity is key. mathc the board trace impedance correctly, terminate appropriateyl , avoid t-stubs or impedance discontinuities ( via's for example ) as they cause refelctions.

if you got good signal integrity you can control edge rate and emc problems go away. trap all energy and it cannot radiate.

But, none of that stuff comes into play if you are dabbling below the 'roughly' 100Mhz range.
just make sure your lines are roughly equal in length and that the 'control' signal governing the write arrives later than the slowest data or address line. that way the signals are already stable before that one arrives.

That is how pci does it. the pci master clock line must be 1.5 inches longer than the longes other pci signal line. this avoids setup / hold problems.

[nctnico]

just make sure your lines are roughly equal in length and that the 'control' signal governing the write arrives later than the slowest data or address line. that way the signals are already stable before that one arrives.

That is how pci does it. the pci master clock line must be 1.5 inches longer than the longes other pci signal line. this avoids setup / hold problems.

PCI actually works because of reflections. Reflections are not always bad!

Like I typed before: the best routing rules depend on the chips being used so always refer to the manual, application notes and datasheets.  I've done loads of PCB designs (some up to several GHz) and there really is no generic recipe that will work for any PCB. I've seen 80MHz SDRAM designs fail due to bad routing because the PCB designer didn't read / understand about routing for SDRAM.

[TripleFault]

Thank you very much Kremmen for that wonderful reply.

I have found that book and have downloaded the Altera doc and will start studying.
I had guessed this subject wasn't easy, but I am determined and there is only one way to learn, and that is by doing.

Thank you very much 

[TripleFault]

Bet you're sorry you asked now TripleFault

What sort of PCB/uC do you have in mind, truth is for the average hobbiest (and even professional) PCB none of this matters, nothing is fast enough.

______
Rob

LOL!
I expected a reply, but Kremmen gave me the encyclopedia.

Basically, I am starting to delve into High Speed uProcessor (200MHZ+) Digital Signal Processing and have noticed all the delays and capacitive loadings on the Buses.
I need to learn all this stuff sooner or later.

Guys like Kremmen make it easier, as they are willing to divest their knowledge to us poor mortals. 

[TripleFault]

It's not until you hit the 200Mhz range that stuff starts getting critical.
If you make sure you daisy chain all nets and you make the rd wr or clock line longer than then longest data/address line you are generally good.
Modern cpu's have controlled slew rates and current mode pin drivers. this already solves a lot of problems. Avoid T-stubs , avoid unneccesarey layer hopping and it will get pretty good.

Now, if you are concerned about EMC , that's another problem...

Thanks for your reply free electron 

Yes, I am going over the 200MHZ mark so i will have to study up on all this.
This is all new territory, so I will have to really go slowly 

[EEVblog]

As has been said, it's really only an issue when you start talking high speed memory (> several hundred MHz).
Look up DDR memory app notes, that's particularly tricky stuff, and one of the most critical, there is plenty of great detail on layout issues.
Not just in terms of length matching, but transmission line termination as well. Because, really, if you have to worry about the length, then you are into transmission line territory.
Micron have some good app notes if memory serves me correctly.

Dave.

[TripleFault]

As has been said, it's really only an issue when you start talking high speed memory (> several hundred MHz).
Look up DDR memory app notes, that's particularly tricky stuff, and one of the most critical, there is plenty of great detail on layout issues.
Not just in terms of length matching, but transmission line termination as well. Because, really, if you have to worry about the length, then you are into transmission line territory.
Micron have some good app notes if memory serves me correctly.

Dave.

Thanks Dave,
It's always good to hear from the master 
I will start reviewing some DDR App notes and muscle up on some transmission line theory.

I hadn't planned on it being an antenna, but oh well it looks like it has become that 

Thanks again Dave,
And maybe you could do a Video Blog on this subject some time, I for one would watch it 

[free_electron]

Micron and samsung have good appnotes on ddr.
It gets really funky when you push into ddr3 territory.... I did a board for the Spear600 ( the same beastie driving dave's scope) processor a while ago... Full of 'curly bits'. we used samsung ram. Series resistors were bot needed but length tuning was.