Typical speed of FPGAs

[gaffer]

I'm about to but a development kit but not sure which one but I'm looking at the MachXO 2280 Breakout Board http://uk.rs-online.com/web/p/programmable-logic-development-kits/7434788/

Can anyone tell me the speed of just 1 logic gate and the speed of 100 in series?
I have a great project in mind and any advice appreciated, I want the fastest.
Thanks

Paul.

[funkathustra]

Can anyone tell me the speed of just 1 logic gate and the speed of 100 in series?

FPGAs don't have logic gates, so I'm not sure what you're asking. Are you talking about input and output buffers on pads?

I have a great project in mind and any advice appreciated, I want the fastest.

You want the fastest FPGA? I think the 16 nm Virtex 7 is probably going to be the fastest (or at least one of the fastest). It has a minimum pad-to-pad delay of 0.288 nanoseconds in the -3 speed grade (obviously from a high-speed LV diff pair — not sure about standard single-ended pads). Most of these have a GCLK that tops out at about 1 GHz, so that should give you an idea of how "fast" they'll be, given you LUT usage, etc.

When you synthesize and fit your VHDL/Verilog design, you'll be able to get timing reports from your FPGA development software. I'm not smart enough to figure that stuff out on my own, so I just let the tools do the thinking for me.

Maybe you should tell us more about your project?

[tggzzz]

Often the gate delay is dwarfed by the interconnection (wire) delay. The latter is highly dependent on where the gates are placed.

So there's no useful answer to your question.

[gaffer]

Can anyone tell me the speed of just 1 logic gate and the speed of 100 in series?

FPGAs don't have logic gates, so I'm not sure what you're asking. Are you talking about input and output buffers on pads?

I have a great project in mind and any advice appreciated, I want the fastest.

You want the fastest FPGA? I think the 16 nm Virtex 7 is probably going to be the fastest (or at least one of the fastest). It has a minimum pad-to-pad delay of 0.288 nanoseconds in the -3 speed grade (obviously from a high-speed LV diff pair — not sure about standard single-ended pads). Most of these have a GCLK that tops out at about 1 GHz, so that should give you an idea of how "fast" they'll be, given you LUT usage, etc.

When you synthesize and fit your VHDL/Verilog design, you'll be able to get timing reports from your FPGA development software. I'm not smart enough to figure that stuff out on my own, so I just let the tools do the thinking for me.

Maybe you should tell us more about your project?

http://uk.rs-online.com/web/c/semiconductors/programmable-logic-circuits/fpgas/

FPGA's  are  programmable logic circuits for And, xor ,nand etc.
I wish to develop my own processor using logic gates but as will require 1000+ gates I looked in to chips that contain many, and came across fpga's.
I really need it as fast as possible, you quoted 0.288 ns. Is this typical? Can I use 100's in series per clock cycle or is it 1 logic per cycle?

http://uk.rs-online.com/web/p/standard-logic-gates/8168797/  for example is a single logic gate chip with a Maximum Propagation Delay Time of 7.5 ns. I would use something like these but soldering 1000+ would take a long time.
I would like faster, if anyone has any advice.
May not be an fpga but intel Pentium processors are like 3.8G a second though not sure if that speed is per thread or total threads?
Thanks.

Just checked out  http://www.analog.com/en/products/high-speed-logic/logic-devices/logic-gates.html
That have a range at 45 Gbps. This is good though I don't want to solder 1000's.
Any advice?
Thanks.

[DaJMasta]

It's really difficult to give you a figure like that, because individual logic gates are not accessible in an FPGA (or if they are, a large chunk of stuff associated with them is disabled and they don't necessarily equate to a normal discrete gate).  It's also a great point that the propagation delay of the individual elements can be a huge hard limit on how fast a complete system can operate - and this applies doubly to trying to build something so complex out of discrete logic.  FPGAs are all about parallelism and building in the elements you need in the quantities you need, and that's where the performance comes from - not just raw clockspeed.

FPGAs are fast enough compared to discrete logic just because of the advantages that a small die and physically close elements can get you that a soft core in an FPGA running at maybe 50MHz or better will outperform identical configuration discrete gates even with optimal layout and high speed gates (and I think that's being pretty generous).  Your pipeline gets long enough that the additional propagation delay through the length of the wires on the board (even if signal integrity and power distribution is fine) is a significant top speed limiter.  Of course, architecture will make a huge speed difference too, and one advantage with an FPGA is that you can reconfigure your architecture to try and optimize performance with just some recompiled software.

You can use 100 gates in series in a single clock cycle in the same way as discrete logic - have a 100 stage pipeline and data processing at every element.  The time it takes for a given piece to get through is still going to be 100 cycles, but you can have 100 pieces of data in there at once.  If you're really that concerned with speed, though, why are you even considering a discrete logic processor?  You're going to be able to hit a few MHz , tops, with discrete parts, so almost any FPGA will likely outperform it.

[MK14]

[chris_leyson]

Until recently I was writing some VHDL for very fast pipelined FFTs which would have gone onto a Zynq7010 or 7020, never got around to finishing the project, company is about to go into administration, but ball park estimate for the high speed parts was 250MHz maybe even 300MHz. Will have to put that project on the back burner for now.

[gaffer]

Just checked out  http://www.analog.com/en/products/high-speed-logic/logic-devices/logic-gates.html
That have a range at 45 Gbps. This is good though I don't want to solder 1000's.
Any advice?
Thanks.

[MK14]

Just checked out  http://www.analog.com/en/products/high-speed-logic/logic-devices/logic-gates.html
That have a range at 45 Gbps. This is good though I don't want to solder 1000's.
Any advice?
Thanks.

EDIT: Cancelled. Please ignore.
At this point, it would seem you are trolling.
If I am wrong, sorry.
If I am right, you have probably been here before ...

[legacy]

the high speed parts was 250MHz maybe even 300MHz

Yup. And we can scale down to 50-100Mhz for hobby.

[legacy]

intel Pentium processors are like 3.8G

CPUs are ASIC design. Completely different in every aspect.
btw, which kind of softcore are you willing to do?

[chris_leyson]

  :-BROKEThanks legacy, I had forgotten about the hobby aspect, but 50MHz to 100MHz is probably about ball park for the lower speed and lower cost FPGAs. I hadn't even checked the prices for the high end Zynq parts let alone the cost of a 500fps camera. Got a few Spartan3 dev boards knocking around and they manage 50MHz with no problems and even 100MHz if you are careful. EDIT: Just read the lattice data sheet, you can STILL do some cool stuff with 2280 LUTs.

[tggzzz]

I wish to develop my own processor using logic gates but as will require 1000+ gates I looked in to chips that contain many, and came across fpga's.
I really need it as fast as possible, you quoted 0.288 ns. Is this typical? Can I use 100's in series per clock cycle or is it 1 logic per cycle?

And when you have developed your own processor, then what? How are you going to program it?

When you say "as fast as possible" do you mean lowest latency or highest throughput or shortest clock cycle?

A CLB delay of 288ps is probably reasonable - and completely irrelevant since the interconnection delays will dominate. It is quite possible that it would take an extra 1000ps for the signal to reach the destination.

I suggest you buy the cheapest FPGA board available, and create some "hello world" applications from beginning to end. That will allow you to explore possibilities and understand constraints. And at that point you will be in a better position to ask questions that can be answered.

[funkathustra]

FPGA's [sic]  are  programmable logic circuits for And, xor ,nand etc.

No, you're mistaken. Yes, they are programmable logic; but they are not "programmable logic gates" — internally, they use look-up tables (LUTs) and digital muxes. This is an extremely basic concept that a sophomore student would learn in the first lecture in their FPGA class. You don't even begin to possess the concepts you'd need to do what you're talking about.

May not be an fpga but intel Pentium processors are like 3.8G a second though not sure if that speed is per thread or total threads?

Completely irrelevant to FPGAs.

Just checked out  http://www.analog.com/en/products/high-speed-logic/logic-devices/logic-gates.html
That have a range at 45 Gbps. This is good though I don't want to solder 1000's. Any advice?

Given the lack of quality in the questions you're asking, I really don't think you have the skill set or experience to work on a project in the manner that you are talking about.

Processors constructed on FPGAs are always going to be much slower and use much more power than an ASIC version of the processor constructed on the same process. Soft-core processors are used in very specific instances when a processor needs to be extended with custom peripherals on the bus, or in research/academic situations. Most modern high-end FPGA-based designs that have processor requirements use a hybrid chip that has both FPGA fabric and a hardware IP processor built-in (usually an ARM processor these days).

If you are interested in learning about implementing processor cores on an FPGA to learn about how they work, there are much better questions to ask. But obviously that's done as a learning exercise; not as a means to actually obtain a fast processor.

Go buy a basic CPLD or FPGA dev board, start working through some basic projects on it, and you'll quickly learn how they work.

[sporadic]

I was really looking forward to some discrete logic 45gbps io processor on a breadboard

Sent from my R1 HD using Tapatalk

[hamster_nz]

Here is a short answer, with millions of assumptions and no real thinking, but just on experience...

On low end FPGAs (Spartan, Artix, Cyclone, Zynq ... ) logically simple designs which do minimal work per cycle (not usually the simplest to design!) can run at more than 300MHz. Lots of pipelining and retiming involved.

Designs that utilise the FPGA's internal architecture features (e.g. us the DSP blocks properly) will run in the mid 200Mhz.

Without lots of work, a video processing pipelines will run at about 150 MHz. It is a big ask going to 300MHz for UHD resolution.

A well designed, moderately complex soft-CPU will clock at around 100 or 150 MHz.

[MK14]

Just checked out  http://www.analog.com/en/products/high-speed-logic/logic-devices/logic-gates.html
That have a range at 45 Gbps. This is good though I don't want to solder 1000's.
Any advice?
Thanks.

Why do you want such potentially huge speed ?
What exactly are you trying to achieve ?

The original Cray 1 supercomputer, is a good example, of perhaps the upper end of how fast a discrete component (limited to small scale logic ICs, ECL), computer might be able to run at.
But bear in mind it was designed by (probably) some of the best in the world computer experts, cost at the time $25,000,000 (much more in today's money) and needed a huge amount of electricity to power it. So much that it needed its own sub-power station.

All the above, gave it around 80 MHz clock speed (with each clock tick = 1 FLOP, with some rare exceptions, making it 2 rarely per clock cycle) (or 160 Million FLOPS peak, which did not apply for most tasks).

Whereas a $10 to $1,000 FPGA based cpu design can easily give you 100 MHz (maybe less) to 500 MHz MIPS (or FLOPS), and probably more than that. Depending on your budget and how competent you are at designing FPGA stuff.

I.e. discrete component cpu, is unlikely to exceed 100 MHz, for a complicated cpu.
But FPGAs can easily get to perhaps 500 MHz or more clock frequency, if the FPGA is of a fast enough type and your design is up to it.

[hamster_nz]

But FPGAs can easily get to perhaps 500 MHz or more clock frequency, if the FPGA is of a fast enough type and your design is up to it.

Oh, and another comparison...

As rough numbers, an Intel CPU core can do approximately 1 billion Multiply-Accumulate operations per second (1G MACS) per core (ignoring SIMD, SSE and so on...). With a US$3,500 E5-2698V4 with 20 cores that makes it 20G MACs peak performance.

I Also have a US$1342 XC7K325T-1FFG900C FPGA around 800 48-bit DSP blocks on it, and they can easily run at 250MHz. It can do 200 billion Multiply-Accumulate operations per second.

That makes it 10x quicker than a 20-core Intel Xeon, and 1/3rd the cost - as long as your algorithms map nicely into an FPGA datapath.

(prices from https://www.amazon.com/INTEL-PROCESSOR-E5-2698V4-2-2GHZ-SMART/dp/B01DTYQHTG and https://www.digikey.com/product-detail/en/xilinx-inc/XC7K325T-1FFG900C/122-1809-ND/2767546)

[joeqsmith]

I'm about to but a development kit but not sure which one but I'm looking at the MachXO 2280 Breakout Board http://uk.rs-online.com/web/p/programmable-logic-development-kits/7434788/

Can anyone tell me the speed of just 1 logic gate and the speed of 100 in series?
I have a great project in mind and any advice appreciated, I want the fastest.
Thanks

Paul.

Hey Paul, welcome to the forum.  Before you buy anything,  I would download some of the free tools and just get a feel without any hardware.  Don't get discouraged. 

I bought a Digilent ARTY board about a year ago to play with the new tools from Xilinx.  It was fairly inexpensive and came with a voucher for the license (really the reason I wanted it).   I setup the tools and went through the tutorials but I have not done anything with it beyond that.   It's pretty amazing what a $100 will get you now days.   

These videos show a few of my early home projects using FPGAs.   This first one shows some early FPGA prototyping boards I made. 


This video shows the larger card running. 


This video shows a couple of reverse print servers I designed.  These basically emulate a Centronics slave port and then dump the data to an Ethernet printer.   This was a pretty fun project.  I wrote the stack in assembler (a real dickhead move according to Dave).   


Good luck with your projects.

[hans]

Also don't pick a too small FPGA. Although some compact cores of a few hundred to maybe a 1000 LE's (Altera) exist, you want to have the extra space of a larger FPGA for routing, peripherals, debug stuff, etc.

Consider also the amount of block RAM available on the FPGA. Some FPGA's don't have ROM sections for program code, and so it needs to be stored in a block RAM. If you only got 16KB of memory, then that's not alot for code+data. Also note that programmers use kB for their firmware, and FPGA datasheets only talk about bits (as you can use block RAM often in data widths of e.g. 2-18 bits).

And yes, the purpose of softcores is purely academical or if you want to add custom peripherals or instructions. I used the NIOS softcore a couple of times on a Cyclone IV FPGA, and it can only run in the 50-100MHz range. The smallest CPU is quite compact, but it does not contain hardware integer multiply/divide. The bigger variants are faster, but a hard-silicon ARM Cortex m3 at same clockspeed will run circles around it.

Finally, if I were to write a softcore CPU myself (plan on doing that someday) I would probably clone an existing architecture so I can make use of their (GCC) compilers.

[chris_leyson]

If you're new to FPGAs and want to build a microprocessor you can learn a lot from this https://www.dc.uba.ar/materias/disfpga/2010/c2/descargas/TechXclusive%20Creating%20Embedded%20Microcontrollers.pdf Someone has taken the time to re-publish the Xilinx Tech Exclusive articles as a pdf "Creating Embedded Microcontrollers (Programmable State Machines)". It describes the Xilinx Picoblaze 8-bit microcontroller for Spartan3 FPGAs and there is even a version for the newer Spartan6 FPGAs. Be warned, the VHDL for the Picoblaze is a structural descripion using Xilinx primatives and not a behavioral description.
Then there is the Lattice Micro8, very similar to the Picoblaze but with several enhancements, it's also free so you could port it to other vendors silicon like Altera or Xilinx.
Do a bit of background reading and then you will get a better understanding of what FPGAs can and can't do efficiently.

[legacy]

the above picture is about a very simple 8 bit integer division implemented in fpga.

I can improve the algorithm to get the result in a shorter time but I have to pay more complexity and area, and the best result I can achieve with an integer division of 32bit  takes 35 clock cycles.

Not so bad, if we look at commercial ASIC solutions

- 41 clock cycles on AMD K7
- 50 clock cycles on Pentium 4 Netburst
- 29 clock cycles on Intel i7 Haswell

the real difference is
- how many LE does it take? a lot on fpga! ASIC uses less silicon
- which is the maximal frequency you can run the algorithm?

ISE v14.3 says @ 140Mhz on Spartan3E-500

[brucehoult]

If you're new to FPGAs and want to build a microprocessor you can learn a lot from this https://www.dc.uba.ar/materias/disfpga/2010/c2/descargas/TechXclusive%20Creating%20Embedded%20Microcontrollers.pdf Someone has taken the time to re-publish the Xilinx Tech Exclusive articles as a pdf "Creating Embedded Microcontrollers (Programmable State Machines)". It describes the Xilinx Picoblaze 8-bit microcontroller for Spartan3 FPGAs and there is even a version for the newer Spartan6 FPGAs. Be warned, the VHDL for the Picoblaze is a structural descripion using Xilinx primatives and not a behavioral description.
Then there is the Lattice Micro8, very similar to the Picoblaze but with several enhancements, it's also free so you could port it to other vendors silicon like Altera or Xilinx.
Do a bit of background reading and then you will get a better understanding of what FPGAs can and can't do efficiently.

Not a bad article, thanks.

I took delivery a week ago of my first FPGA board, an Arty Z7-20. It's probably got far more resources than I'll ever use with 53k 6-input LUTs, but you never know. It was only $50 more than the -10 with one third of the resources, and I had the $50. ($200 vs $150 vs $99 for original Arty without the ARM cores (which I may or may not end up using)

Primarily I want to play with different soft CPUs, ranging from historic ones to Linux-capable RISC-V or similar. However I've been busy with other things in the last week and didn't yet get Vivado to the point of being able to get a simple blinky or "press button, LED turns on" working yet.

[hans]

[..]

the above picture is about a very simple 8 bit integer division implemented in fpga.

I can improve the algorithm to get the result in a shorter time but I have to pay more complexity and area, and the best result I can achieve with an integer division of 32bit  takes 35 clock cycles.

Not so bad, if we look at commercial ASIC solutions

- 41 clock cycles on AMD K7
- 50 clock cycles on Pentium 4 Netburst
- 29 clock cycles on Intel i7 Haswell

the real difference is
- how many LE does it take? a lot on fpga! ASIC uses less silicon
- which is the maximal frequency you can run the algorithm?

ISE v14.3 says @ 140Mhz on Spartan3E-500

Also note that designing for FPGA's and ASIC's require slightly different strategies. In ASICs a flipflop is more expensive, in FPGA's you get them basically for free because if you're using the LUT the LE can also be configured to use the flip-flop (use or bypass).

Any project there is always the trade-off area, power and speed. You can basically implement multiply and division if you got an ALU than do (signed) add, subtract, shifts and some kind of immediate management. In last semester for a master college project we implemented a datapath that used the 'shift and add' multiply and long division. It worked out quite well, not perfect, watch out with those -128 * -128 multiplications  And same as you, it also took 35-40 cycles per operation to complete.

Just for kicks I did a straight multiply/divide in VHDL using 32-bit operands. I think it resulted in about 15k LE generated just for that operation. Whoops! I think our complete CPU only took like 3k LE, although that was still quite mediocre.

[suicidaleggroll]

I bought a Digilent ARTY board about a year ago to play with the new tools from Xilinx.  It was fairly inexpensive and came with a voucher for the license (really the reason I wanted it).

FYI - that voucher is pretty pointless.  All of the Xilinx Artix models are covered under the free Webpack license, which does basically everything Design Edition does:
https://www.xilinx.com/products/design-tools/vivado/vivado-webpack.html

[legacy]

Yup.

"booth" is another interesting algorithm composed by parallel multipliers for integer signed numbers.

Formally it computes MAC (multiply and accumulate), in this way

z = (x*y) + u

u: n+1 bits
x: n+1 bits
y: m+1 bits
z: n+m+1 bits

It's interesting because it can boosted by DSP slices if your fpga happens to have them available 

[legacy]

15k LE generated just for that operation. Whoops!

eheheh, I had the same shock when I tried to implement a modified version of "bkm".

I have been researching a good way to calculate the complex exponential of a complex number, since the result is interesting!

ans=cmplxexp(x0.re, x0.im)

With a pure imaginary part (x0.re = 0), you get a trigonometric couple of function, { cos(phi), sin(phi) }
With a pure real part (x0.im = 0), you get the real exponential

Combining them you can get hyperbolic functons, { cosh(phi), sinh(phi) }
Manipulating them you can get the square root, logarithm, tan, tanh, etc, etc

It's a very powerful block of math which offers a lot of function-implementations!

But! It's damn complex, unstable(1), and even staying with the whole arithmetic was fixed point, QN8.24, the algorithm requires nine huge LUT full of values of pre- calculated function sampled at specific points, plus a lot of correction value to help the algorithm to stay stable.

In short it consumes a lot of BRAM.

(1) this problem has been solved recently (with not formally) with an accelerant serie accelerating the convergence at the cost of introducing distortions. You need a control accelerant serie to smooth them, but it works stable, and it's damn fast!

32bit data size? it takes 32 clock cycles! And you get the result on the 33th!

Bad news: it also consumes a lot of multiplier and adder, and a lot of logic. Something like 20K LE (definitively too much area!!!), with a maximal speed of 130MHz on my Spartan3E

~ ~ ~ ~ ~ ~

Reading papers, I discovered that Intel has a similar technology implemented in their CPU starting from 80487. It was BKM-base, but their papers were never published as they are "industrial secrets". So, I wonder how did they solved the convergence problem? And how did they implemented it without wasting an area of silicon that, in my case, on fpga, it would take five time the area of the whole CPU_core ?

Intel is a commercial company. There will be no answer to my questions, neither their modified BKM algorithm will be published or explained in details.

A pity, but that's life 





Conclusion:
since I need to implement the whole softcore, and since it eats resources, I am limited about resources available for the Math-(fixedpoint)-CoProcessor, thus I am implementing a soft version of Cordic, which just computes the two most used trigonometric functions: { COS, SIN }.

In the future, I will try to put the modified-BKM inside a dedicated fpga, like if it was a "80487" companion chip 

[joeqsmith]

I bought a Digilent ARTY board about a year ago to play with the new tools from Xilinx.  It was fairly inexpensive and came with a voucher for the license (really the reason I wanted it).

FYI - that voucher is pretty pointless.  All of the Xilinx Artix models are covered under the free Webpack license, which does basically everything Design Edition does:
https://www.xilinx.com/products/design-tools/vivado/vivado-webpack.html

I think when I had checked into it, the ILA was not included.

[rstofer]

For the Artix 7, Xilinx has published timing specs

For the definitions - the CLB definitions start at page 58

https://www.xilinx.com/support/documentation/user_guides/ug474_7Series_CLB.pdf

For the values - see page 27 for details about the CLBs themselves, not including anything else in the path:

https://www.xilinx.com/support/documentation/data_sheets/ds181_Artix_7_Data_Sheet.pdf

I have no idea what to do with that information.  Timing is probably swamped in routing and unless I spend a lifetime figuring out how the routing algorithm works, there probably isn't a lot I can do about it.  What I could do is define my project in terms of CLBs and place the CLBs where I think is best and then let the router make the interconnects.  Or, I can just hope that Xilinx knows best how to synthesize, place and route.

I'm going to take the easy way out and let the toolchain do the work.  My major CPU project runs at 50 MHz and it wouldn't be a stretch to get it to 100 MHz.  The CPU isn't pipelined in any way and it is a straightforward implementation of the instructions, as described in the original documentation.  The original computer, released in '65, ran at about 400 kHz.  I'm running 125x and all of the original software runs unaltered.

That's the real issue:  Software!  So you have this really great CPU, but do you have a native operating system, compilers, macro assembler, file system, input and output peripherals and an entire library full of application code?  If not, why build it?  If the CPU doesn't evolve into a fully function SYSTEM, why bother?

BTW, the way you beat delay accumulation is to pipeline.  Do a small it of work and register the result.  The following stage uses data in the register to do a small bit of work and registers that result.  It's a PITA to work out the details but that's the way you get speed.

As a first approximation to FPGA speed, look at the price.  There a reason that Xilinx Virtex devices cost more than their Spartan devices.  Part of it is speed, part of it is BlockRAM size and a lot of it is IO functionality.  At some point, increases in CLB propagation delays simply aren't possible so the manufacturers try other ideas to get overall throughput up.

[rstofer]

I bought a Digilent ARTY board about a year ago to play with the new tools from Xilinx.  It was fairly inexpensive and came with a voucher for the license (really the reason I wanted it).

FYI - that voucher is pretty pointless.  All of the Xilinx Artix models are covered under the free Webpack license, which does basically everything Design Edition does:
https://www.xilinx.com/products/design-tools/vivado/vivado-webpack.html

I think when I had checked into it, the ILA was not included.

Yes, the ILA feature is included, even in the WebPack edition.  I have run a couple of examples and, if I could ever figure out the constraints file, it might be a useful tool.

The other nice thing about Vivado WebPack is that it includes a lot of IP cores including Microblaze and several peripherals including everything required to implement Ethernet.  Not every Microblaze peripheral is included and in some cases there are limitations.  One example is that 100 Mb Ethernet is included free, 1000 Mb is not.

For those who have used Eclipse and the GNU toolchain, the SDK will have a comfortable feel.  I haven't spent any time with the System Debugger other than to note that it holds the CPU in reset until the Run button is pushed (on the SDK) and the UART communicates with the SDK console (or any other terminal application), or, at least it does on the Digilent Nexys4 DDR board.

I'm not too sure how fussy Xilinx is about the voucher.  I'm about to find out since I am building a new PC to accommodate Vivado.  The process of regenerating the block layout and creating a bitfile is truly grim on my Quad Core 2.8 GHz I7 680.  I can't afford REAL speed but I thought a Quad Core 4.2 GHz I7 1770K would be a step up.  Theoretically, I can overclock that chip up to 5 GHz so Vivado would only be half as grim.  Still grim, but only half as grim as it is today.

I was looking at the new AMD Ryzen Threadripper 1950X 16 core 32 thread chip (what a beast!) but Vivado will only use 8 threads and I don't do a lot of multitasking so what's the point?  Still, sweet chip!

I really miss ISE  (sigh)...  And, yes, it's still installed to support my Spartan 3 projects.

[brucehoult]

The other nice thing about Vivado WebPack is that it includes a lot of IP cores including Microblaze and several peripherals including everything required to implement Ethernet.  Not every Microblaze peripheral is included and in some cases there are limitations.  One example is that 100 Mb Ethernet is included free, 1000 Mb is not.

I'm hoping/assuming one can use those ethernet and DDR memory etc IP blocks with your own designs, not only MIcroblaze (or ARM in the case or Zynq).

The process of regenerating the block layout and creating a bitfile is truly grim on my Quad Core 2.8 GHz I7 680.  I can't afford REAL speed but I thought a Quad Core 4.2 GHz I7 1770K would be a step up.  Theoretically, I can overclock that chip up to 5 GHz so Vivado would only be half as grim.  Still grim, but only half as grim as it is today.

Assume you mean 860, not 680. I build a machine with one of those in January 2010. It was damn nice at the time, easily thrashing an 8 core 2.26 GHz Mac Pro I'd been loaned before it for pretty much everything. I overclocked it to 3.44 GHz base speed (3.6 speedstep). Geekbench3 10625 https://browser.geekbench.com/geekbench3/332494

I went from that to a 4790K, geekbench3 around 18000, so a big step up https://browser.geekbench.com/geekbench3/1160100

And then after I moved countries and didn't take that still very decent machine with me, I've built a 6700K, geekbench3 20300 https://browser.geekbench.com/geekbench3/5266295

Not that big a step from the 4790K to the 6700K, but it ends up near to twice the speed of the 860.

The really big step was from Nehalem to Ivy Bridge. It's only been tweaks since then.

[rstofer]

Just for kicks I did a straight multiply/divide in VHDL using 32-bit operands. I think it resulted in about 15k LE generated just for that operation. Whoops! I think our complete CPU only took like 3k LE, although that was still quite mediocre.

But you can get 18x18 signed multiply in a single cycle by using the internal multipliers.  No such help for the division.  It took me a very long time to find the algorithm for non-restoring signed 32/16 division.  I finally found it is a book that just so happened to include pseudo microcode.  I just translated it and its been working since.

I must be dense; I just couldn't wrap my head around some of the published algorithms.  Too darn old...

For the Spartan 3, Xilinx has a document about multipliers and at page 6, describes a 35x35 design that looks like it requires 3 stages of pipelining.  Of course, if there are a lot of things to multiply, they still get a new result on every clock.

https://www.xilinx.com/support/documentation/application_notes/xapp467.pdf

Division is just plain hard.

[rstofer]

In terms of Vivado, here's a link to most of the reference material.  There will be a test later!

https://www.xilinx.com/products/design-tools/vivado.html?resultsTablePreSelect=documenttype:SeeAll#documentation

[joeqsmith]

I bought a Digilent ARTY board about a year ago to play with the new tools from Xilinx.  It was fairly inexpensive and came with a voucher for the license (really the reason I wanted it).

FYI - that voucher is pretty pointless.  All of the Xilinx Artix models are covered under the free Webpack license, which does basically everything Design Edition does:
https://www.xilinx.com/products/design-tools/vivado/vivado-webpack.html

I think when I had checked into it, the ILA was not included.

Yes, the ILA feature is included, even in the WebPack edition.  I have run a couple of examples and, if I could ever figure out the constraints file, it might be a useful tool.

Now, but again I don't believe it was included in the early releases.

I was looking at the new AMD Ryzen Threadripper 1950X 16 core 32 thread chip (what a beast!) but Vivado will only use 8 threads and I don't do a lot of multitasking so what's the point?  Still, sweet chip!

That is strange, my voucher license allows for 12.   Is this a limit of the Webpack?   Maybe they removed the limit with the newer release.

[rstofer]

OK, right off the bat, I am not an expert on Xilinx licensing!  Even doing version upgrades terrifies me because I know I will need to get a new license and although the web site is vastly improved, it is still far from intuitive.  But it works!  At least it has so far.  I just need to remember to include the checkbox for ISE 14.7 so license file covers both platforms.

Looking at the Digilent site, I don't see any reference to the voucher.  I wonder if that is a thing of the past?

I agree, I don't think ILA was available early on.  I'm not sure how much of the IP was available either.  The fact that a simulator is included in the WebPack is quite a step up from ISE.  I don't use simulation but it's nice to know it is there.

At some point, Xilinx realizes they are in the chip business, not the software business.  I think the are beginning to loosen up.  I realize they have a dumpster load of money involved in creating Vivado but that was then, this is now.  It's a sunk cost, get over it!  Get the software out there, it's not like it helps your competitor.  The more people are talking about it, the more sales will eventually follow (except in my case).  Especially make student versions available.  Graduates tend to bring what they know.

I haven't been a big fan of Vivado.  It is terribly slow, attention span shattering slow, VASTLY slower than ISE but maybe with more CPU horsepower I can overcome that.  The workflow is pretty smooth and once I get more comfortable with the IDE, I'm sure I'll start to like it a lot more.

And I don't understand TCL.  I have no idea how to create an XDC file!  I think I may actually have to read a manual.  Manuals are boring!  I can copy and paste signal definitions but when adding the ILA, I have no idea what I am doing.  The IP automation helps with some of it but I recall having to mess around in there to get it to work.  Time to hit the books!

[joeqsmith]

In terms of Vivado, here's a link to most of the reference material.  There will be a test later!

https://www.xilinx.com/products/design-tools/vivado.html?resultsTablePreSelect=documenttype:SeeAll#documentation

Just install DocNav.

OK, right off the bat, I am not an expert on Xilinx licensing!  Even doing version upgrades terrifies me because I know I will need to get a new license and although the web site is vastly improved, it is still far from intuitive.  But it works!  At least it has so far.  I just need to remember to include the checkbox for ISE 14.7 so license file covers both platforms.

Looking at the Digilent site, I don't see any reference to the voucher.  I wonder if that is a thing of the past?

Yes, I believe they now reference the webpack.  If they really limit the number of CPUs with the webpack as you suggest, that seems like a miss on their part because again, I do not see a limit with the voucher license. 

I agree, I don't think ILA was available early on.  I'm not sure how much of the IP was available either.  The fact that a simulator is included in the WebPack is quite a step up from ISE.  I don't use simulation but it's nice to know it is there.

For the most part I was using a third part simulator until iSim.  The new version with Vivado is fairly nice.  Still no code coverage from the little I played with it but looks like they have made some good progress with it over the old ISE.  Watching it simulate a fairly long run now.  I need to download the 2017 chain.  I am just playing with the 2015 for now.
 

At some point, Xilinx realizes they are in the chip business, not the software business.  I think the are beginning to loosen up.  I realize they have a dumpster load of money involved in creating Vivado but that was then, this is now.  It's a sunk cost, get over it!  Get the software out there, it's not like it helps your competitor.  The more people are talking about it, the more sales will eventually follow (except in my case).  Especially make student versions available.  Graduates tend to bring what they know.

I've been hearing these sort of comments for 20 years now.  Things have changed. Some of the early Altera CPLD tools (DOS based schematic) were going to be well out of the reach of a hobbyist.  Things have really improved for us.  Third party simulators have had analog view for some time.  Screen shot of the sim I am currently running.  I went through the GPIO and microblaze Ethernet demos but then starting working on my own.  I'm still at the blinking LED stage but making some progress.  Really just trying to learn the basic flow with the simulation and ila.  The actual ARTY board just sits there.  Need to hook a scope up to it or something.     

I haven't been a big fan of Vivado.  It is terribly slow, attention span shattering slow, VASTLY slower than ISE but maybe with more CPU horsepower I can overcome that.  The workflow is pretty smooth and once I get more comfortable with the IDE, I'm sure I'll start to like it a lot more.   

And I don't understand TCL.  I have no idea how to create an XDC file!  I think I may actually have to read a manual.  Manuals are boring!  I can copy and paste signal definitions but when adding the ILA, I have no idea what I am doing.  The IP automation helps with some of it but I recall having to mess around in there to get it to work.  Time to hit the books!

I agree about the execution times of Vivado but that seems to be the norm with most tools I use.  Of course the PCs get faster and the capability of the tools improves.

[joeqsmith]

Woke up and it actually made it through the test script without crashing.  A little over 2 hours to simulate.  Not bad. Using the analog feature appears to slow down the waveform viewing. 

Adding the ila also seems to add a fair amount of time but at least for this very simple design, seems to work fine when looking at the three LED outputs. 

I have seen the tool crash.  A friend of mine told me how the MIG will crash if running under Win10.  I was able to replicate the fault.  Running the tools under Win 7 seems to be fine, which I verified as well.  They are running two PCs.  Generating the MIG under Win7, then loading the results onto the newer PC to work around the problem.

Attached the scope to the Arty's LEDs using 10X probes and the 6" ground clips. To the untrained eye, it's a little hard to tell this looks anything like the simulation or ila.     Maybe its time to move beyond the blinking LEDs.  The Arty has some controlled differential pairs. 

[joeqsmith]

Still the flying leads but at least its not off the LEDs and now you can make out the waveform patterns.    

Really not a bad board for getting your feet wet with the tools. 

[rstofer]

It's a good thing I didn't know that the MIG would crash on Win 10.  The Microblaze EchoServer example at Digilent used the MIG to interface with the DDR and it runs all code from the DDR.  I built it using Vivado 17.2 on Win 10.

Not to say there isn't some condition(s) under which it croaks under Win 10 but at least for that particular experiment MIG worked fine.

[joeqsmith]

It's a good thing I didn't know that the MIG would crash on Win 10.  The Microblaze EchoServer example at Digilent used the MIG to interface with the DDR and it runs all code from the DDR.  I built it using Vivado 17.2 on Win 10.

Not to say there isn't some condition(s) under which it croaks under Win 10 but at least for that particular experiment MIG worked fine.

Maybe 17.2 corrected it.  If you want to give it a try, open the MIG generator.  Just use the defaults until you reach the select the Pin/Bank menu and select Fixed.   Now select Read XDC/UCF.   Let me know what happens.

[rstofer]

It's a good thing I didn't know that the MIG would crash on Win 10.  The Microblaze EchoServer example at Digilent used the MIG to interface with the DDR and it runs all code from the DDR.  I built it using Vivado 17.2 on Win 10.

Not to say there isn't some condition(s) under which it croaks under Win 10 but at least for that particular experiment MIG worked fine.

Maybe 17.2 corrected it.  If you want to give it a try, open the MIG generator.  Just use the defaults until you reach the select the Pin/Bank menu and select Fixed.   Now select Read XDC/UCF.   Let me know what happens.

I don't know what to expect.  I don't get any opportunity to set defaults or select Read XDC.

I created a new project and then used "Create Block Design" to add the mig_7 gadget.  I got only a box with clock and reset signals.  Then I added a Microblaze and ran "Run Block Automation".  Finally, the mig had the other signals and a bus connection to the DDR.  I right clicked on DDR2 and clicked 'Make External' to bring those signals out of the FPGA.

I need to study up on board.prj files because most of the pin definitions are in this file and are provided, in this case, by Digilent.

I know it all works out because the Digilent Echo Server runs.  The only .XDC file in the source tree is eth_ref_clk.xdc which I created and contains only a definition for the ethernet reference clock output.

I suspect I didn't address what you were aiming for.  In any event, nothing bad happened and Vivado seems quite happy.

[joeqsmith]

No problem.  You don't need to do anything really beyond opening the IP Catalog and run through the MIG.  No need to play with the Microblaze or other IP.    If you wanted to just play with their Ethernet Echo demo, just open the block diagram, select the MIG and customize.  Again, just go through the menus until you get to the pin selection and then select the Read XDC/UCF.  It's going to warn you about overwriting your settings but go ahead.  What happens?   

[rstofer]

No problem.  You don't need to do anything really beyond opening the IP Catalog and run through the MIG.  No need to play with the Microblaze or other IP.    If you wanted to just play with their Ethernet Echo demo, just open the block diagram, select the MIG and customize.  Again, just go through the menus until you get to the pin selection and then select the Read XDC/UCF.  It's going to warn you about overwriting your settings but go ahead.  What happens?

Error message "Failed to generate IP 'mig_7series_0'.  Failed to generate 'Custom UI' outputs

[joeqsmith]

If you have Windows 7 with Vivado installed, you could try the same steps and see what happens. If everything repeats, you will get a different result. 

[rstofer]

I do have a version of Vivado on Win 7.  I'll give it a try tomorrow.  I doubt that it is version 2017.2 but maybe....

[joeqsmith]

We have tried 2017.2 16.3 and 15.2.  These all behaved the same on the two OS's.   

[rstofer]

OK, I got an error attempting to customize the IP when using Win 10 that doesn't seem to be a problem with Win 7.

That is regrettable!  I hope Xilinx gets it worked out fairly soon.

From my perspective, it may not be an issue.  MIG does work with the Microblaze for the Nexys4_DDR using the various automations- that is a given.  Digilent also offers a DDR component for the Nexys4_DDR that makes the DDR memory look like SRAM.  I will create a dummy project in the near future to see if the component works under Win 10.

My project probably uses a configuration very much like the EchoServer.  The difference is that I need 4 or 5 open ports and some way to get the streams out of the Microblaze and into my VHDL project.  That is yet to be determined.  Apparently it is non-trivial.

I am buying a much faster computer specifically for Vivado (plus some other tools).  I planned to use Win 10 but I guess I can still buy Win 7 on the 'grey' market.

[joeqsmith]

If you go to a better computer, it will be interesting to see if the webpack is still locked on the number of cores it allows you to select.  They do only show you the max for your PC.  So if you have 1 core, they only show the option to select one.   Maybe that's why the webpack seems limited. 

[rstofer]

I ran some tests on my 3.2 GHz I7-860 quad core machine and, indeed, Vivado WebPack uses 8 logical processors.  It is consistent with the info in the linked manual, Page 7.

Synthesis doesn't seem to use multiple threads (and it shouldn't) but the other processes use all 8 as they should.

Place and route keep the CPU pretty busy.  Synthesis only uses about 18% but that's probably right because it only uses one thread.

I did notice that when the load gets high (80%+), the CPU throttles back from 3.2 GHz to 2.9 GHz.  Not the kind of thing I would have anticipated.

The new machine will be a 4.5 GHz I7-1770K with 32 GB of 4133 MHz DDR4.  I don't plan to overclock it but it is known to run at 5 GHz.  Cooling being an issue...

The big difference in the new machine is a SSD PCIe x4 with 1TB of room.  I have great hopes for this, especially at boot time.

AFAICT, 8 logical processors is all that Vivado will use.  I was looking at the AMD 16 core 32 thread chip but if Vivado won't use all the threads, why bother?

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2016_1/ug904-vivado-implementation.pdf

[NorthGuy]

My computer with Vivado installed has CPU overheat warning buzzer. When Vivado gets busy, it is buzzing non-stop. If you're building a computer for Vivado, you may consider some sort of after-market cooling (liquid cooling perhaps) especially if you want to overclock.

It is ridiculous that Vivado is so slow. Although Xilinx says it's "SuperFast". Go figure.

[joeqsmith]

I ran some tests on my 3.2 GHz I7-860 quad core machine and, indeed, Vivado WebPack uses 8 logical processors.  It is consistent with the info in the linked manual, Page 7.

Synthesis doesn't seem to use multiple threads (and it shouldn't) but the other processes use all 8 as they should.

Place and route keep the CPU pretty busy.  Synthesis only uses about 18% but that's probably right because it only uses one thread.

I did notice that when the load gets high (80%+), the CPU throttles back from 3.2 GHz to 2.9 GHz.  Not the kind of thing I would have anticipated.

The new machine will be a 4.5 GHz I7-1770K with 32 GB of 4133 MHz DDR4.  I don't plan to overclock it but it is known to run at 5 GHz.  Cooling being an issue...

The big difference in the new machine is a SSD PCIe x4 with 1TB of room.  I have great hopes for this, especially at boot time.

AFAICT, 8 logical processors is all that Vivado will use.  I was looking at the AMD 16 core 32 thread chip but if Vivado won't use all the threads, why bother?

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2016_1/ug904-vivado-implementation.pdf

Right.  With Vivado loaded, select the Design Runs tab.  Right click inside this menu and select Launch Runs.   Select the number of jobs. 

[joeqsmith]

Quick and dirty probes for the Arty.     

[brucehoult]

I did notice that when the load gets high (80%+), the CPU throttles back from 3.2 GHz to 2.9 GHz.  Not the kind of thing I would have anticipated.

Why? That's exactly the kind of thing you expect when the TDP is hit.

The new machine will be a 4.5 GHz I7-1770K with 32 GB of 4133 MHz DDR4.  I don't plan to overclock it but it is known to run at 5 GHz.  Cooling being an issue...

What the heck is a 1770K?

[ebastler]

The new machine will be a 4.5 GHz I7-1770K with 32 GB of 4133 MHz DDR4.  I don't plan to overclock it but it is known to run at 5 GHz.  Cooling being an issue...

What the heck is a 1770K?

Intel i7-7700K, I assume?

[brucehoult]

The new machine will be a 4.5 GHz I7-1770K with 32 GB of 4133 MHz DDR4.  I don't plan to overclock it but it is known to run at 5 GHz.  Cooling being an issue...

What the heck is a 1770K?

Intel i7-7700K, I assume?

The current mainstream high end, yes. But 1770K has been repeated several times in different messages.

So far the 6700K is doing all I need and I've only had it 18 months.

[rstofer]

The new machine will be a 4.5 GHz I7-1770K with 32 GB of 4133 MHz DDR4.  I don't plan to overclock it but it is known to run at 5 GHz.  Cooling being an issue...

What the heck is a 1770K?

Intel i7-7700K, I assume?

Yes...  The AMD is the 17xx

All typos are mine!

[rstofer]

I did notice that when the load gets high (80%+), the CPU throttles back from 3.2 GHz to 2.9 GHz.  Not the kind of thing I would have anticipated.

Why? That's exactly the kind of thing you expect when the TDP is hit.

I thought about that.  It's hard to tell just how hard the processor is working without actually measuring temperature.  I don't have a convenient way to do that on the old CPU.  The new motherboard should have utilities for that kind of thing since folks have a tendency to seriously overclock the chip.

I suppose if an application is going to drive a CPU to the thermal limit, Vivado or ISE would be the ones to do it.  I don't have any other apps that create a long duration run.  Maybe some of my grandson's games...

I need to look into improving the cooling system.

[brucehoult]

I did notice that when the load gets high (80%+), the CPU throttles back from 3.2 GHz to 2.9 GHz.  Not the kind of thing I would have anticipated.

Why? That's exactly the kind of thing you expect when the TDP is hit.

I thought about that.  It's hard to tell just how hard the processor is working without actually measuring temperature.  I don't have a convenient way to do that on the old CPU.  The new motherboard should have utilities for that kind of thing since folks have a tendency to seriously overclock the chip.

I suppose if an application is going to drive a CPU to the thermal limit, Vivado or ISE would be the ones to do it.  I don't have any other apps that create a long duration run.  Maybe some of my grandson's games...

I need to look into improving the cooling system.

Try "Handbrake" aka a GUI wrapper around ffmpeg.

I haven't tried the 7700K but on earlier generations the stock cooler from Intel is not good enough to prevent thermal throttling below the advertised SpeedStep levels under heavy load. Get a 3rd party one. You don't need anything exotic: anything from Noctua or CoolerMaster in the US$30 - $100 range is fine.

[rstofer]

Try "Handbrake" aka a GUI wrapper around ffmpeg.

I haven't tried the 7700K but on earlier generations the stock cooler from Intel is not good enough to prevent thermal throttling below the advertised SpeedStep levels under heavy load. Get a 3rd party one. You don't need anything exotic: anything from Noctua or CoolerMaster in the US$30 - $100 range is fine.

It's my understanding that Intel doesn't provide a cooler for the 7700K.

http://www.tomshardware.com/answers/id-3364162/bad-stock-cooler-7700k-overclock.html

Coolers turned into an Amazon 'review' nightmare.  It didn't matter which cooler I looked at, somebody was complaining that a) it was damaged in shipment b) no customer support c) didn't cool d) package was opened, obvious returned goods, etc.  Every single one! Now, I do take reviews with a grain of salt and some users should stick to playing with ball bearings but when the % gets above single digits, I start to pay attention.

So I bought the Cooler Master MasterLiquid Pro 240.  I don't know how it will turn out and I decided that I don't care.  If my first attempt doesn't work out, I'll just do it over.

http://www.coolermaster.com/cooling/cpu-liquid-cooler/masterliquid-pro-240/

One of the problems with ordering a bunch of parts is not knowing exactly how much space is available for the CPU cooler.  An example of a surprise: the Corsair Vengeance DDR4 comes with a snap-on fan that mounts over the top of the sticks and necessarily determines the clearance requirements for the bottom of the CPU cooler.  It shouldn't have been a surprise if I had researched a little more but it's a good thing I bought a liquid cooler for a first cut.

I'm expecting surprises when I mount the cooler to the CPU and when I mount the radiator to the case.  I have no idea how that's going to turn out.

Sometimes you just don't know what you don't know!

[joeqsmith]

If you are not familiar with the ARTY board, connectors JA&D use 200 ohm series resistors.  The small interface board I made uses 450 ohms to get me the 10X.  This is why I started out with 3.5ish and get 2.5ish.   

JC&D use zero ohm jumpers rather than the 200 ohms.   I changed over to connector JC, then added an MMCM to drive the clock.   Simulation seems to work fine with the MMCM.   Lots of little steps but getting more comfortable with the tool set.   

[brucehoult]

Liquid cooling seems overkill. A decent air cooler is much simpler to fit, more reliable, and will keep the temperature well under 100C under even the heaviest loads.

Trying to keep the temp down to under 90, under 80 etc is just a for of cooler masturbation. You won't keep a computer long enough to hurt the CPU at 100 C.

People of course disagree over relative merits of brands. I've been pleased with Noctua 12, 14, 15 (depending on socket or case size or whatever). Not the cheapest, but not crazy expensive, and they are easy to fit and definitely do the business. So I haven't bothered to try anything else.

[rstofer]

One advantage the liquid cooler has is that the appendage over the CPU is much smaller in every dimension.  I don't have the motherboard, I don't have the case, I didn't know about the RAM fan, etc.  I didn't really want to go with liquid cooling (still don't) but, of the choices I could make, with what little I knew at the time, it seemed like the safest thing to buy.

It may very well turn out that one of the air coolers will fit just fine.  But I didn't know that at the time I ordered the parts.  Once I see how everything fits together, I may just order one of the better air coolers.  Coolers are inexpensive so changing to air at a later date is certainly possible.

The choice of liquid cooling was never about temperature (to me).  It was somewhat related to noise but mostly I wanted the best chance of everything fitting in the case the first time I tried.

[joeqsmith]

Looks like the slew rate and drive strength all work.  Shown with all four set to fast and slow and sweeping the drive strength.  These are all set to LVCMOS33 which would normally default to slow/12.

One thing I have been unable to find is if I drive the constraints from an XDC file, I can't find a way to combine multiple properties on a single line like with a UCF.   I have not found any mention of this in the documents.  They always seem to show one line per property.    It throws an error on every attempt I made.   Not a big deal, just a little strange.  Other than that, the tools still look pretty good. 

The scope I have been using is only 600MHz, not to mention the home cobble probe board.  I was surprised the 600MHz signal even showed up in the one plot. 

[rstofer]

This is known to work and combines pin number and drive level

Code: [Select]

set_property -dict { PACKAGE_PIN D5    IOSTANDARD LVCMOS33 } [get_ports { eth_ref_clk }]; # Sch=eth_ref_clk

This came from a Digilent Nexys4_DDR Echo Server project:
https://reference.digilentinc.com/learn/programmable-logic/tutorials/nexys-4-ddr-getting-started-with-microblaze-servers/start

I'm pretty sure the -dict { ... } allows a list of options but I sure didn't find a document that confirms it.

[joeqsmith]

This is known to work and combines pin number and drive level

Code: [Select]

set_property -dict { PACKAGE_PIN D5    IOSTANDARD LVCMOS33 } [get_ports { eth_ref_clk }]; # Sch=eth_ref_clk

This came from a Digilent Nexys4_DDR Echo Server project:
https://reference.digilentinc.com/learn/programmable-logic/tutorials/nexys-4-ddr-getting-started-with-microblaze-servers/start

I'm pretty sure the -dict { ... } allows a list of options but I sure didn't find a document that confirms it.

That's a good find.  I just tried 

set_property -dict { PACKAGE_PIN U12 SLEW SLOW DRIVE 4 IOSTANDARD LVCMOS33 }

and indeed this works.  In Docnav, searching for -dict yields no results.  But Google did not let me down:
https://www.xilinx.com/support/answers/62465.html

Searching for just "dict" in docnav, the UG903 Vivado Design Suite User Guide Using Constraints

The Tcl dict command can be used to build a dictionary (associative array) of cells and
absolute grid RLOCs for the update_macro command. A Tcl associative array is a series of
key-value pairs. The cells and RLOCs can be arranged as such as series using the dict
command. The array keys are the macro cell objects. The array values are the cell RLOCs.
This helps to automate the process of creating macros with many cells.

[joeqsmith]

Still having fun with the Arty.   This new board for the Arty has a differential driver.   The FPGA core is just a diff buffer and forwards the signal to an output.   Shown with the differential input near 600MHz.   I have not tried to simulate the differential input. 

[joeqsmith]

I had just assumed that Digilent would have provided jumpers to allow you to set the VCCO voltages to allow use of some of the various standards.  Sadly, not the case and all banks are stuck at 3.3V.   The LVDS input is no problem as Xilinx allows it  with a 3.3V as long as you are not using the internal termination (which is how I show it).  But for an LVDS output, they are tri-stated if the voltage exceeds 2.85.   The 3.3 is used for other devices like the Ethernet, so that idea is out.   

The RF signal is divided by two, so I am clocking it at 700MHz.     

Still a fun little board to play with and it may be useful for some quick and dirty experiment.  Time to play with the SDK.   

I would like to get something with an UltraScale device to play with.

[rstofer]

 

Still a fun little board to play with and it may be useful for some quick and dirty experiment.  Time to play with the SDK.   

The Echo Server demonstrates the entire process from block design through to the SDK where everything is compiled and the executable jammed into the bitfile.  All of the code runs out of DDR memory with nothing more than a bootloader running out of BlockRam.

I have done this project for the Arty and the Nexys4_DDR.  Both worked well when I actually did what the instructions said to do.  Freestyle might not be the best approach!

[joeqsmith]

 

Still a fun little board to play with and it may be useful for some quick and dirty experiment.  Time to play with the SDK.   

The Echo Server demonstrates the entire process from block design through to the SDK where everything is compiled and the executable jammed into the bitfile.  All of the code runs out of DDR memory with nothing more than a bootloader running out of BlockRam.

I have done this project for the Arty and the Nexys4_DDR.  Both worked well when I actually did what the instructions said to do.  Freestyle might not be the best approach!

I worked the demos back on the first page when I first started playing with the board.   As you suggest, just follow the simple instructions and no problems.