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Understanding ARM startup code (__scatterload stuff)

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Looks like a licensing problem. Armclang has tons of optional features controlled by a huge license config file - code size restrictions, various optimization options enabling, output formats restrictions etc.


--- Quote from: westfw on October 20, 2021, 08:12:05 pm ---For CM23, I'd start to expect that some build environments would have some support for the "trustzone" features that ARM is pushing.  Maybe adding overrun protection to the stack in addition to "just set SP to some place in memory", and/or "protecting" un-allocated memory.

--- End quote ---
Funny you are mentioning this - it seems the TrustZone is optional for Cortex M-23 - https://developer.arm.com/ip-products/processors/cortex-m/cortex-m23
And I cannot figure out whether it is implemented in my GD32E230 or not  :-//

Looking at the datasheet - https://gd32mcu.21ic.com/data/documents/shujushouce/GD32E230xx_Datasheet_Rev1.3.pdf - it only mentions this:

--- Quote ---* Internal Bus Matrix connected with AHB master, Serial Wire Debug Port and Single-cycle
IO port
* Nested Vectored Interrupt Controller (NVIC)
* Breakpoint Unit(BPU)
* Data Watchpoint and Trace (DWT)
* Serial Wire Debug Port
--- End quote ---

If I compared with the datasheet of the GD32E505 f.x. which has a Cortex M-33 (also with optional TrustZone) - https://www.gigadevice.com/datasheet/gd32e505xxxx-datasheet/ - this one mentions a lot more like the DSP, FPU, MPU and ITM f.x. which are all optional for Cortex M-33.

So my guess is since the TrustZone is not mentioned anywhere it is not implemented in neither of these MCUs?

It looks like even "baseline" ARMv8 have some non-optional stack limit checking:
--- Quote ---The simplest ARMv8-M implementation, without any of the optional extensions, is a Baseline implementation, see [color=rgb(7.000000%, 7.000000%, 80.100000%)]ARMv8-M variants [/color][/font][/size][/color][color=rgb(7.000000%, 7.000000%, 80.100000%)]on page A1-27[/color]. The ARMv8-M Baseline offers improvements over previous M-profile architectures in the following areas:
* The optional Security Extension.
  An improved, optional, Memory Protection Unit (MPU) model.
  Alignment with ARMv8-A and ARMv8-R memory types.
  Stack pointer limit checking.
  Improved support for multi-processing.
  Better alignment with C11 and C11++ standards.
  Enhanced debug capabilities.
--- End quote ---
I am, alas, not surprised that the 76-page datasheet you have is not very complete WRT the information it provides :-((although I've really come to like the section I've seen in SOME datasheets where they go "here are the Cortex-M0+ configuration options, and how they've been set in the particular chip.   It doesn't seem very common, though.  :-( )


This https://www.gigadevice.com/press-release/gigadevice-launches-low-cost-gd32e230-mcu-series-featuring-the-cortex-m23-generation-core/[/url] GD32E230 launch note says “Subsequent products can also benefit from TrustZone® technology”, so it looks like “not this time”.

@westfw: Ha ha yes that would be perfect :)
And just FYI the stack limiting in Cortex M-23 is obligatory in the Secure Mode (if TrustZone is implemented), and not at all possible in non-Secure Mode (or without TrustZone). In M-33 you have MSPLIM and PSPLIM for non-secure mode.

@abyrvalg: well spotted - that confirms it then  ;)


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