Unexpected voltages from a 3.3V CMOS clock: why?

[technix]

On my Duplex Mini 2 board, the clock used by the A3P060 FPGA is generated from the main STM32F103TBU6 MCU, using its MCO clock output feature. However here is something a bit unexpected: that clock has some unexpected voltages on my scope, while both chips has a 3.35V supply voltage (VDDIO for the FPGA,) the clock signal has a strange shape and a VPP at about 5V.

The clock signal in question runs at 36MHz, which doesn't sound that fast. The signal comes out of the MCU as 3.3V LVCMOS push-pull output, immediately hop down to the bottom layer for about 10mm, and pop up immediately next to the FPGA pin. The board is 1.6mm double layer FR4.

1) Why?
2) Does the fact the FPGA has nothing written in it matters?
3) Will this stress my FPGA? By how much?
4) How do I eliminate this?

[asmi]

On my Duplex Mini 2 board, the clock used by the A3P060 FPGA is generated from the main STM32F103TBU6 MCU, using its MCO clock output feature. However here is something a bit unexpected: that clock has some unexpected voltages on my scope, while both chips has a 3.35V supply voltage (VDDIO for the FPGA,) the clock signal has a strange shape and a VPP at about 5V.

Can you post a screenshot from your scope? It sounds like ringing.

The clock signal in question runs at 36MHz, which doesn't sound that fast. The signal comes out of the MCU as 3.3V LVCMOS push-pull output, immediately hop down to the bottom layer for about 10mm, and pop up immediately next to the FPGA pin. The board is 1.6mm double layer FR4.

It has been said a million times - the frequency doesn't matter for SI, what matters is how sharp fronts are (dV/ns).

1) Why?

Massive impedance mismatch.

2) Does the fact the FPGA has nothing written in it matters?

It might depending on the state IO buffers are when it's not configured. On Xilinx FPGAs there is a pin that controls that, check your FPGA's documentation for more details on this.

3) Will this stress my FPGA? By how much?

Depending on current transients it might've killed IO buffers and/or ESD protection diodes.

4) How do I eliminate this?

Add serial termination resistor to reduce ringing. Start from 100 Ohms and adjust it as needed to make sure fronts still stay sharp while most of ringing is gone. As additional radical measure you can add a pair of fast Shottky protection diodes (one from signal trace to Vccio, another one from ground to signal trace, such that these would "chop off" over- and undershoots. Also if possible, try reducing the strength of the output driver.

Or simply move to 4 layer board with matched traces impedance.

[asmi]

But before you do all of that, make sure that the signal you're seeing on a scope actually exists there, and not just introduced by your scope's probe. Use proper high-speed measurement technique with a ground clip - none of that crocodile ground lead rubbish.

[technix]

But before you do all of that, make sure that the signal you're seeing on a scope actually exists there, and not just introduced by your scope's probe. Use proper high-speed measurement technique with a ground clip - none of that crocodile ground lead rubbish.

I took that measurement with that alligator clip and a short piece of wire for grounding... I wonder why impedance mismatching can cause such gross overshoots?

[Siwastaja]

You can think about it in two ways: Energy is stored in the parasitic LC network, or based on transmission line theory, as reflections, whichever suits you.

Overshoot can be as much as 100% in worst case, and can easily break things. This is also bad for EMI.

It's not as much about impedance matching, even more importantly, it's about edge rate control. Meaning, you have quite a lot of (multi-)gigahertz content there you don't need for your slow fundamental 36MHz clock. Filter the high-frequency content away (meaning: smooth the edges to be less sharp). To do this, you add series resistance, which acts as RC filter together with the receiver's parasitic capacitance.

Or, you can think it as a transmission line thing. Your source sends the wave. The wave reflects back at the end. Right at that moment, the voltage at the destination is exactly correct (thanks to this reflection). But the wave keeps going, and reflects again from the source. And again, and again. In such point-to-point links with a single destination, series termination (resistor at the source) is typically the way to go. A resistor equivalent to your trace impedance eats the reflections. Now, assuming a 8 mil trace on a 1.6mm 2-layer board, your trace impedance is 145 ohms.

Put some 100-200 ohms there and see what happens.

Too much, and your clock edges will be so slow it either stops working completely, or is more susceptible to noise and jitter.

How long is your trace? I'm surprised you are having such a large issue if the board is very small. Maybe the MCO output is unnecessarily strong; I don't remember if it can be adjusted or not (like the IOs can with the OSPEEDR register), but if not, the external resistor is the only option.

[Bassman59]

On my Duplex Mini 2 board, the clock used by the A3P060 FPGA is generated from the main STM32F103TBU6 MCU, using its MCO clock output feature. However here is something a bit unexpected: that clock has some unexpected voltages on my scope, while both chips has a 3.35V supply voltage (VDDIO for the FPGA,) the clock signal has a strange shape and a VPP at about 5V.

The clock signal in question runs at 36MHz, which doesn't sound that fast. The signal comes out of the MCU as 3.3V LVCMOS push-pull output, immediately hop down to the bottom layer for about 10mm, and pop up immediately next to the FPGA pin. The board is 1.6mm double layer FR4.

1) Why?
2) Does the fact the FPGA has nothing written in it matters?
3) Will this stress my FPGA? By how much?
4) How do I eliminate this?

Unless the route between the MCU and the FPGA is totally borked, this should work.

An unconfigured ProASIC3 device's I/O pins are all tristate so they won't damage the driver in the micro or themselves. They are even designed for cold-sparing so voltages on their inputs when unpowered will not cause damage.

Things to check include making sure that your FPGA clock input pin is really an I/O and not a power-supply pin or other specialist pin.

[David Hess]

Make sure that your oscilloscope probe's compensation is set correctly.

[technix]

How long is your trace? I'm surprised you are having such a large issue if the board is very small. Maybe the MCO output is unnecessarily strong; I don't remember if it can be adjusted or not (like the IOs can with the OSPEEDR register), but if not, the external resistor is the only option.

The trace is less than a centimeter long and it doesn’t have vias at all. STM32F1 doesn’t have OSPEEDR, only 2MHz/10MHz/50MHz driver strength options, and I need that 50MHz driver to allow me run the clock at 36MHz.

[Siwastaja]

A centimeter long trace really shouldn't show that much ringing. It's well possible that it's caused by the measurement and isn't actually present.

[technix]

A centimeter long trace really shouldn't show that much ringing. It's well possible that it's caused by the measurement and isn't actually present.

This is what happened when I re-probed it using the ground spring using a nearby cap as the grounding point instead of the alligator clip.

[tggzzz]

But before you do all of that, make sure that the signal you're seeing on a scope actually exists there, and not just introduced by your scope's probe. Use proper high-speed measurement technique with a ground clip - none of that crocodile ground lead rubbish.

I took that measurement with that alligator clip and a short piece of wire for grounding... I wonder why impedance mismatching can cause such gross overshoots?

With a croc clip and wire for a ground connection, there's no need to invoke or consider "impedance mismatch": simple lumped inductance is sufficient.

For the basic theory and a practical example, see https://entertaininghacks.wordpress.com/2015/04/23/scope-probe-accessory-improves-signal-fidelity/ and https://entertaininghacks.wordpress.com/2016/09/17/scope-probe-accessory-higher-frequency-results/ You may, or may not, find some of the other links on those pages helpful.

[asmi]

This is what happened when I re-probed it using the ground spring using a nearby cap as the grounding point instead of the alligator clip.

Well there you go. There is still some ringing, but it's much more under control. I'd still add a serial termination for the future revision, but more importantly you've learnt a good lesson about measurements - sometimes a mere attempt to measure signal changes it so much that the measurement results don't make any sense.

[technix]

This is what happened when I re-probed it using the ground spring using a nearby cap as the grounding point instead of the alligator clip.

Well there you go. There is still some ringing, but it's much more under control. I'd still add a serial termination for the future revision, but more importantly you've learnt a good lesson about measurements - sometimes a mere attempt to measure signal changes it so much that the measurement results don't make any sense.

So a 49.9 ohm resistor in the middle of the trace?

[Siwastaja]

Series termination is always as near as the driving source as possible, and the resistance should be equivalent to your transmission line impedance (use a microstrip impedance calculator online; it will be somewhere around 150 ohms for a 2-layer board). Subtract your driver's output impedance from this to get the external resistor value. For standard CMOS, you can assume 20 ohms and it's close enough typically.

This as a design advice, if you need to do something similar in a case where transmission line analysis is appropriate; i.e., something much longer (and/or much higher edge rates).

With your short trace, and now with properly measured scope screen, it seems you don't have any problem here, the edge rate already seems limited (although it might be due to your scope's limited BW as well...) and there is almost no ringing, so it doesn't matter too much if you use a resistor at all, or what value, or where you put it. The bigger the value, the more it smooths the edge rate down. Now, going for "real" impedance control doesn't make a lot of sense on 2-layer board, as the impedance is high and the resistor value needs to be high, and this may slow down the edges too much.

[tggzzz]

This is what happened when I re-probed it using the ground spring using a nearby cap as the grounding point instead of the alligator clip.

Well there you go. There is still some ringing, but it's much more under control. I'd still add a serial termination for the future revision, but more importantly you've learnt a good lesson about measurements - sometimes a mere attempt to measure signal changes it so much that the measurement results don't make any sense.

So a 49.9 ohm resistor in the middle of the trace?

Search for "transmission line termination" and "LC step response" and all will be explained - without people here spending their time and (poorly) recapitulating that information.

Read https://www.edn.com/collections/4435129/Bogatin-s-Rules-of-Thumb starting at number 0; that kind of information can avoid the "but I was told that would work" kind of excuse.