VHDL using algorithmic architecture

[Fantasma25]

Hello, I'm starting to make my own projects using a Basys2, and I see a lot of cool examples using algorithmic coding in their architectures (using process(), instead of a block diagram with descrete components), but my professor once told me that that kind of architecture declaration is not very recommended, since the software that is used to sinthesize the circuit may need to create black holes and break the space-time continuous in order to sinthesize the circuit, and get it wrong. What are your experiences? Should I loose the fear of using a process()? Thank you!

[AndyC_772]

I think you should ask your professor what he was smoking, and whether he has any left.

[Fantasma25]

Lol! I'll ask him. He is rather old, so that's probably why he says that (although I may have exaggerated with the black holes). So it's safe to go for the process?

[RPKH]

Lol! I'll ask him. He is rather old, so that's probably why he says that (although I may have exaggerated with the black holes). So it's safe to go for the process?

Yes. In VHDL that is basicly the only way to go.
This site can be of some help to you. http://www.fpga4fun.com/HDL%20tutorials.html

[Kohanbash]

Using process is a basic technique that is used in most designs. There is no reason to fear it.

My only caution is to be careful with the sensitivity list. Having the wrong things in there can cause problems. If is often best to keep it simple and then add an if statement at the beginning of the process to catch particular states.

[zapta]

Several years ago I had to venture at work into VHDL programming. One very bright and experienced engineer looked at my code and gave me two advices

1. Make everything synchronous.
2. Use functional programming style (e.g. each variable is assigned exactly once).

For example:

wire count_end  = (counter >= (N - 1));
counter <= Reset ? 0:
    count_end? 0:
    counter + 1;

I followed his advice and everything went really smooth.

If I got it correctly, your professor recommend #2 above.

[Neilm]

1. Make everything synchronous.

The trouble with making everything synchronous is that you will lose one of the main advantages of an FPGA over small micros. I have never had an issue making some things asynchronous.

I would definitely agree that each variable should only be assigned once.

[nkavv]

Hi Fantasma25, Neilm and all

First, a parenthesis: Fantasma25 (ancient Greek "fasma"; literally spectre in Greek; meaning ghost) an interesting choice of name.

The trouble with making everything synchronous is that you will lose one of the main advantages of an FPGA over small micros. I have never had an issue making some things asynchronous.

Indeed I often choose to collapse dependent operations within the same clock cycle. This is a form of operation chaining. It might lower your critical path, but it usually pays in overall execution time.
I would say that in practice I have 2x-3x time gains with it. You also save some registers.

I would definitely agree that each variable should only be assigned once.

Second that. My first thought on this idea from functional programming is the Appel paper (SSA is functional programming). Actually it is a good idea to code in an SSA-ish style.

Best regards
Nikolaos Kavvadias
http://www.nkavvadias.com

[zapta]

... First, a parenthesis: Fantasma25 (ancient Greek "fasma"; literally spectre in Greek; meaning ghost) an interesting choice of name.

Reminds me the My Big Fat Greek Wedding movie. The father loved to explain the greek origin of words.  ;-)  Great movie.

What do you mean by collapsing multiple operations in the same clock cycle?  Just doing more complex logic function between the register stages? If so, it is still100% synchronous.

[nkavv]

Reminds me the My Big Fat Greek Wedding movie. The father loved to explain the greek origin of words.  ;-)  Great movie.

Hope you've enjoyed, I'm more of scifi, action, thriller kind so still need to watch the whole movie and not only in bits.

What do you mean by collapsing multiple operations in the same clock cycle?  Just doing more complex logic function between the register stages? If so, it is still 100% synchronous.

Yes, you got me there. I also wouldn't use handshakes/acknowledgement, better to go with synchronous interfaces where possible.

There is an under-referenced technical report by a student of Prof. Gajski, about Modeling custom hardware in VHDL. It describes FSMDs (Finite State Machines with Datapaths) that using asynchronous handshakes. However, never used these techniques, they might be ill-suited to FPGAs.

There is also a well-known project on an asynchronous toolchain by Univ. of Manchester. And once there was an asynchronous ARM, AMULET (?), don't know if this went into production.

A Greek research institute had also made an asynchronous DLX (ASPIDA) synthesizable core. The prime minister at the time paid them a visit or so at an exhibition.

That's all.


Best regards
Nikolaos Kavvadias
http://www.nkavvadias.com

[marshallh]

The thing about timing analysis tools for FPGAs is they are designed around all synchronous logic. You can force them off at your own risk (these days by default the timing analysis is actually used in the synthesis stage and also to determine P&R constraints) but it's going to be an academic exercise at most