If I was building a ROM-less Z80 with a hardware loader/debugger, I'd want to be able to write-protect areas of the RAM, maybe in 8K pages (because that can be done conveniently with a 3 to 8 line decoder, an 8 switch DIP switch and an 8 input AND), and I'd probably add battery backup to the RAM (assuming its SRAM).
Using the other 64K of the RAM is more complex. A crude paging scheme that swaps the remaining RAM into the top 32K of the memory map is possible without much extra logic, but if you want a more capable MMU that can realistically support CP/M+ or MP/M, take a look at Obiwanjacobi's design.
Another useful facility is to decode a small block of I/O addresses to force the Z80 into a wait state and interrupt the PIC. You also need a tristate buffer between the PIC and the data bus activated by the decoded I/O address ORed with /RD, so the Z80 can grab data from the PIC after the PIC releases the wait state. That lets you implement peripherals in the PIC as software, sniffing the Z80 bus, and have them appear as hardware to the Z80. As the PIC has two USARTs and two MSSP peripherals, it would be possible to implement a buffered serial port, and SD card interface with minimal extra hardware.