Using 3.3 MCU to switch 5V circuit with p-ch mosfet. What are the pitfalls?

[eTobey]

Hi,

i want to power another circuit with 5V and a p-ch mosfet, but i have a 3.3V MCU. I made up this circuit, and i think it is safe for the MCU. The little current, that would result can safely drained over the internal diodes of the MCU, am i right?

Cheers,
Toby

[langwadt]

depends on the MCUs io structure, if it has a diode to 3.3V the mosfet might never turn off

[SiliconWizard]

It would also always leak current to the MCU when the MCU itself is not powered, which may or may not happen depending on your use case. But if the 5V may be present when the 3V3 isn't, and you need the MCU to be off in that case (rather than in a odd state trying to start), that's going to be a potential problem. May also cause issues just if you want to minimize power draw in some "sleep" mode.

So I'd suggest just controlling the PMOS via a NMOS, which will solve all this.

[fchk]

Won't work.

A PMOS turns on if gate is more negative than source.
A PMOS turns off if gate is equal to source or more positive.

Your uC can output at max 3.3V, so the PMOS will never turn off. Your uC could switch the gate pin to Input or Hi-Z. Then the pullup will brig the gate to source potential, but this is a slow process and therefore not recommended. A MOS transistor has very little losses when completely turned off or completely turned on. Staying in the gray region for an extended period of time will generate losses and heat. Don't do this. The gate is basically a capacitor, and you need current to charge and discharge the gate capacitance fast enough in order to avoid losses.

The best way is using a load switch. Example:
https://www.diodes.com/assets/Datasheets/AP22652_53_52A_53A.pdf

+ good for up to 2.1A
+ built-in current limiter (no suffix) or latch-off protection (A suffix)
+ backflow protection. Current can only flow from in pin to out pin, but never backwards from out to in.
+ A 3.3V uC can drive the EN pin without problems. (Vh>=1.5V)
+ uses NFET instead of PFET. You want to avoid PFETs and use NFETs wherever possible because the charge mobility of electrons is MUCH MUCH higher than the charge mobility of holes. NFETs always have better properties and lower losses. The load switch has got a charge pump for generating the 10-15V required for fully turning on the internal pass NFET.
+ cheap (0.4€) for what it does.
+ internal fault detection (overcurrent, short circuit,...)

If 2A is not enough there are load switches with 6A, 12A or more current.

Or when using an external NFET there are gate drivers that have built-in charge pumps and can provide enough current to drive large FETs (up to several Amps).

[magic]

With rare exceptions, like the RESET pin of AVRs, pins are diode clamped to VCC so P-MOSFET gate voltage will never rise above 3.3V+0.6V = 3.9V and it will remain somewhat conductive.

So I'd suggest just controlling the PMOS via a NMOS, which will solve all this.

And the simplest way of doing it is: gate to 3.3V, source to the GPIO, drain to the gate of the P-MOSFET.

[woofy]

The selected FET has a threshold of 0.9v (0.5 to 1.3v) so with 1.7v bias it will leak current when off. Use SiliconWizards suggestion above and drive it with an NMOS.

[Ian.M]

The O.P's circuit requires a 5V tolerant I/O pin on the MCU.  To turn on, set as output low. to turn off, first set as output high to get the gate up to 3.3V quickly^* then a few microseconds later, set as input to allow the pullup resistor to get it all the way up to 5V (0V Vgs).  The optimum dwell time at output high depends on the I/O pin drive capability and the MOSFET gate charge.  As fchk points out, a high resistance pullup is *slow* so if the min.gate threshold voltage is under 1.7V, you need to figure out how long it will take to get from 3.3V up to 5V-Vgs_threshold, and check that the total transition including the output high dwell time wont transiently violate the SOA at max. load current.  If it looks marginal, decrease the pullup resistance.

If you haven't got a 5V tolerant I/O pin, take the good advice above and *DON'T* use this circuit.  In addition to the MOSFET not turning off properly, passing current through the I/O pin protection diodes can cause malfunction. e.g. disturb ADC results on other pins, internal reference voltages and internal oscillator frequencies.    IIRC on some of Microchip's PICs even 1% of the abs. max. input pin clamping current could cause a 40% oscillator frequency shift!

* Edit: If a lower value pullup is used that can discharge *all* the gate charge quickly enough, go straight to input mode to turn off.

[langwadt]

With rare exceptions, like the RESET pin of AVRs, pins are diode clamped to VCC so P-MOSFET gate voltage will never rise above 3.3V+0.6V = 3.9V and it will remain somewhat conductive.

most pins on an STM32 is Vcc +4.0V

So I'd suggest just controlling the PMOS via a NMOS, which will solve all this.

And the simplest way of doing it is: gate to 3.3V, source to the GPIO, drain to the gate of the P-MOSFET.

depends on whether you want inverting or not, though your common gate might have a slightly faster turnoff via the body didoe

[eTobey]

The best way is using a load switch. Example:

After reading through the comments, i think this is really the best way. The current limiting is something that could really help too.
And one less item to place and less space beeing occupied. Oh wait... it needs heaps of components for just a "switch".

Thanks a lot!

[JPortici]

In these cases, depending on the load, i either use a high side/load switch (which may come with some advantages as zero current flow when off - which would require two antiseries mosfets -, current limited soft switching for inrush current, and current limit, some even with current measurement build in)
or a dual N+P mosfet and three resistors when cheap is fine.
Gate of PMOS biased at +5V using resistor, and connected to drain of NMOS.
Gate of PMOS connected to drain of NMOS.
Gate of NMOS biased at GND using resistor.
Gate of NMOS connected to MCU GPIO using resistor.

[eTobey]

Can i use this loadswitch without its components?

I created this with mosfets. Does it have any flaws?
Link

[Kleinstein]

The principle idea is OK, but the capacitor is not helping and making the circuit slow. A small FET may not like slow turn on/of when the current is high.
The resistors are a bit on the high side and alread slow down the ciruit. For a really low power circuit it may still be OK.

[Ian.M]

I wouldn't trust that Falstad sim further than I can spit upwind in a gale!  How does the gate of the driver N-MOSFET discharge when you open the switch?  In real life if you leave a gate floating it tends to retain its previous voltage (and thus state) for a while, but eventually leakage is likely to take it into its linear region, which in turn is likely to slowly sweep the high side P-MOSFET through its linear region, and unless its got an excessively large DC SOA and decent heatsinking, blowing it.

Edit: Confirmed - The Falstad MOSFET models are borked and have zero gate charge!  In the O.P's sim, plot the current through the series gate resistor,  confirm you see the capacitor charge/discharge, then remove the capacitor and the gate charge/discharge current goes to zero . . .   

@eTobey:  Learn to use a SPICE simulator - LTspice is popular here.  Its free unless you are a semiconductor manufacturer, has a reasonably comprehensive set of device models, and there's a lot more third party ones that either are for it or are compatible with it.

[PCB.Wiz]

Can i use this loadswitch without its components?

I created this with mosfets. Does it have any flaws?

That dual-device is the safe/easy way to manage level shifting. 
You can get dual mosfet packages with P + N mosfets, or dual digital transistors, with PNP + NPN parts.

Your original design, might work if
a) you have a MCU with 5V tolerant IO pins. (ones that can pull up to 5V)
or
b) You choose a P-FET with a deliberately high VGS, so that the 1.7V difference is not enough to turn on the FET  (AO3401 is not suitable, with a typ VGS of 0.9V)

[SiliconWizard]

If using 5V-tolerant IOs, and after checking in the DS what is exactly meant by 5V-tolerant for this chip, then you should just configure the GPIO as open drain. Do not even try setting it to 1 in a totem-pole configuration (normal output mode) to shut down the PMOS, as others have explained, it may not work, wether the IO is 5V-tolerant or not, and is useless anyway.

[eTobey]

I think its a good idea, to not have the mosfet switch on too quickly? I have about 1m of cable to the circuit taht would be powered. And i guess it has 20-50uF capacitors in total.
I dont want to get glichtes in my MCU.

Yes the falstad is kinda only a toy, but i really like the simplicity for simple things.

Can anyone give me an example of the dual package? couldnt find those.

BTW: There is nothing more to say about my original design.

[Siwastaja]

As others have said, a "5V tolerant" pin which has "open drain" mode available. If such pin is not available, then add extra N-MOSFET to drive the high side P-MOSFET. Two transistors instead of one, but not that bad.

[woofy]

Can anyone give me an example of the dual package? couldnt find those.

G300C03L6
But I wouldn't bother with nichey stuff like that. Separate NMOS/PMOS transistors are dirt cheap and available everywhere.
Is your I/O pin 5v tolerant?

Edit to add a few more:
https://uk.farnell.com/w/c/semiconductors-discretes/fets/dual-mosfets/prl/results?channel-type=complementary-np-channel|np-channel&range=inc-in-stock&sort=P_PRICE

[JPortici]

Can anyone give me an example of the dual package? couldnt find those.

G300C03L6
But I wouldn't bother with nichey stuff like that. Separate NMOS/PMOS transistors are dirt cheap and available everywhere.
Is your I/O pin 5v tolerant?

Edit to add a few more:
https://uk.farnell.com/w/c/semiconductors-discretes/fets/dual-mosfets/prl/results?channel-type=complementary-np-channel|np-channel&range=inc-in-stock&sort=P_PRICE

niche... not really, if you look at the various catalogs you have several hundreds of different models, all pin compatible and basically interchangeable for this specific purpose
and even then when you have 100s of thousands availability, it is really a jellybean part

[fchk]

The best way is using a load switch. Example:

After reading through the comments, i think this is really the best way. The current limiting is something that could really help too.
And one less item to place and less space beeing occupied. Oh wait... it needs heaps of components for just a "switch".

Thanks a lot!

Want fewer parts? TPS2065DVBR. Fixed current limit. 100nF capacitors on input and output. !OC can be left open when overcurrent signal is not needed.

[PCB.Wiz]

Can anyone give me an example of the dual package? couldnt find those.

For BJT they call these pre biased or digital transistors
One vendor's examples
https://www.nexperia.com/products/bipolar-transistors/resistor-equipped-transistors-rets/#/p=1,s=0,f=c57601:a5e17,c=,rpp=,fs=0,sc=c543b7,so=des,es=
Dual Pre Biased BJT allow this with a single, low cost part, up to a few hundred mA.
If your loads are into the Amps, you should use NMOS/PMOS pairs.

[langwadt]

Can anyone give me an example of the dual package? couldnt find those.

For BJT they call these pre biased or digital transistors
One vendor's examples
https://www.nexperia.com/products/bipolar-transistors/resistor-equipped-transistors-rets/#/p=1,s=0,f=c57601:a5e17,c=,rpp=,fs=0,sc=c543b7,so=des,es=
Dual Pre Biased BJT allow this with a single, low cost part, up to a few hundred mA.
If your loads are into the Amps, you should use NMOS/PMOS pairs.

BJT is also going to have some voltage drop

[NorthGuy]

Why not to switch on the low side with N-FET?