FPGA timing requirements

[gauravmp]

Hi,

I keep getting a few errors stating that the timing requirements were not met. I'm using Vivado and an Artix-7 device. Could someone please let me know what sources I have to refer to to get acquainted with timing specifications and how I could meet them.

Thanks

[Sal Ammoniac]

Vivado Design Suite User Guide - Design Analysis and Closure Techniques

[gauravmp]

Thanks a lot for the help man!