As i work in an international company : european designers are all vhdl , while all the stuff we do in the us is indeed verilog.
In the end it doesn't matter. everyone is responsible for a block. if they synthesize they synthesize. there are translator tools and the synthesizers like synopsys don;t care. they eat anything.
Verilog requires a lot less keyboard pounding than VHDL.
There are contests between VHDL and Verilog. you get a problem and 30 minutes to code it. VHDL always fails in these contests ( they are organised by the Synopsis users group). The veriloggers finish design and testbench while the VHDLlers are still stuck correcting the typo's in their source... to get it to synthesize.
i personally hate VHDL because some of the required keyboard pounding and a couple of really annoying things like having to create intermediate signals. if x is defined as an output you cannot write x = x+1 as you can't directly read from the output. that is simply stupid.
Verilog was always designed as a language to model logic from the beginning..
VHDL was an afterthough bolted on to HDL. HDL can be used to describe anything , analog , digital , mechanical , system assemblies. as long as you create definitions you can do anything. that is why , when writing logic you need to load those two IEEE libraries. those files define what is a logic one , what is a zero , what is an unknown , what is a tristate , weak pull up and their interrelations. it also describes to operators and their relationship. without those libraries HDL does not know about logic. there are libraries for analog , even to describe how two piece of metal are bolted together with a screw.
One key thing that never seems to be mentoined between VHDL and Verilog is that the one is strong typed and the other one is not.
If you're design an ASIC or silicon, you need to be goddamn know well what you're doing & typing, and what that (intermediately) translates to, when you're doing Verilog. I've learned VHDL first and wanted to learn the Verilog "dialect", but was immediately put off by this. It reminds me back in the old days I was writing PHP and Python, where there is no consistent way of telling what is what, or what output is yielded from which operation (and whether the types are consistent & correct).
An example: if I have a std_logic_vector which I want to "Cut up and paste together" , I can write something like this:
my_vector_2 <= my_vector_1(7 downto 1) & "00";
Great I've zero-ed the 2 LSB bits of that byte. If I put 1 bit too less or too much on this new vector, VHDL will prompt an error and say that the widths don't match.
In my little experience with Verilog, it didn't say that for me, and that implicit typing means you can do some really messy things, or miss bugs, or require extra synthesis steps to find out bits are undefined. It may be what you want if you're very experienced & clever, but for all other purposes I like the toolchain to point me at things even if it means I'm treated like a baby-coder.