Verilog newbie help

[jeremy]

Hi guys,

I've been trying to learn verilog lately, and my latest project is to build a serial port echo device. I'm a bit stuck working out how to proceed to the next stage of my design.

I've tested both RX and TX modules separately and they work just fine (I'm using the ones from here). I am having trouble putting together a one-shot system that will trigger the data transmit. Basically, RxD_data_ready is high when the module is not receiving data, so I'd like to pulse the transmit line. However, every time I try to implement a flag like has_sent_data, I get multiple driver errors. I understand why these are there, but I don't really know how to get around them. Can anyone give me a hint?

My current code is attached (snipped a little to keep it short):

Code: [Select]

wire ready_to_read = rxd & ~txd_busy;

async_receiver asr(.clk(clk), .RxD_data_ready(rxd), .RxD_data(rxd_data), .RxD(avr_tx));
async_transmitter ast(.clk(clk), .TxD_start(txd_start), .TxD_data(led), .TxD(avr_rx), .TxD_busy(txd_busy));

always @(ready_to_read)
begin
led <= rxd_data;

if (has_sent == 0)
begin
has_sent <= 1'b1; // this is the multiple driver problem
txd_start <= 1'b1;
end
end

always @(posedge clk)
begin
if (current_data != rxd_data)
begin
has_sent <= 1'b0; // this is the multiple driver problem
current_data <= rxd_data;
end
end

[codeboy2k]

Instead of the always@(ready_to_read) block, why not just move all that down into the always@(posedge clk) block and test for ready_to_read with a simple if statement.  It will be synchronous to the clock now, and no more multiple drivers.

[jeremy]

Yep, that fixed it. I suppose that thinking about it now, the rxd signal is synched with the clock anyway...

[codeboy2k]

Yep, that fixed it. I suppose that thinking about it now, the rxd signal is synched with the clock anyway...

Good that it fixed it.  Yes, I was thinking the same too.. that at least one of the two signals rxd or txd_busy was already synchronous to the clock anyways, so just bring it all into the one process block synchronous to the clk edge.