also the following doesn't work under ghdl

`library IEEE;`

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

...

constant XLEN : integer := 32;

subtype cpuWord is std_logic_vector(XLEN -1 downto 0);

...

when alu_add =>

res <= opa + opb + (getStdLogicVectorZeroes(XLEN-1) & cin);

` use IEEE.STD_LOGIC_ARITH.ALL;`

use IEEE.STD_LOGIC_UNSIGNED.ALL;

those libraries are NOT defined in ghdl and can't be used easily

therefore the "+" operator is not defined for std_logic_vector

and the attempt to simulate "opa + opb" will result an error

instead you need to use

`library ieee;`

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

along with the following ugly code

` when alu_add =>`

result <= std_logic_vector

(

unsigned(opa) + unsigned(opb) +

unsigned(getStdLogicVectorZeroes(XLEN-1) & cin)

);

work <= std_logic_vector

(

unsigned("0" & opa) + unsigned("0" & opb) +

unsigned(getStdLogicVectorZeroes(XLEN-1) & cin)

);

in this case "unsigned(opa) + unsigned(opb)" is allowed

because the "+" operator is defined along with unsigned

but the result needs to be std_logic_vector

both the above pieces of code come from OpenCores

therefore I assume it's a common trouble

edit:

`entity ALU_arithmetic is`

Port

(

enable : in std_logic;

-----------------------

opa : in cpuWord;

opb : in cpuWord;