Abstract
Alliance is a complete set of free cad tools and portable libraries for vlsi design. It includes a vhdl compiler and simulator, logic synthesis tools, and automatic place and route tools. A complete set of portable cmos libraries is provided. Alliance is the result of a twelve year effort spent at SoC department of LIP6 laboratory of the Pierre & Marie Curie University (Paris VI, France). Alliance has been used for research projects such as the 875 000 transistors StaCS superscalar microprocessor and 400 000 transistors ieee Gigabit HSL Router.
allianceDoes anyone happen to use it?
It might be used as simulator.
Tried today from the git-repository.
It seems it comes with limited vhdl-features, e.g. it seems it doesn't support library and generic port.
btw, the following worked
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity priority_encoder is
port
(
in_data : in std_logic_vector (7 downto 0);
out_data : out std_logic_vector (3 downto 0)
);
end priority_encoder;
architecture behavioral of priority_encoder is
begin
process (in_data)
variable first_one: std_logic:=0;
begin
first_one:= '0';
out_data<=(others=>'0');
for i in in_data'range loop
if ((not first_one) and (in_data(i)='1')) then
first_one:='1';
out_data<=std_logic_vector(to_unsigned(i,out_data'length));
end if;
end loop;
end process;
end behavioral;
priority_encoder_2.vhd
with this pat file
--port list
--inputs
in in_data (7 downto 0) X;;;
--outputs
out out_data (3 downto 0) X;;;
begin
--Signal list
< 0 fs> : 00 ?0 ;
< 20 fs> : 01 ?0 ;
< 20 fs> : 02 ?1 ;
< 20 fs> : 04 ?2 ;
< 20 fs> : 08 ?3 ;
< 20 fs> : 10 ?4 ;
< 20 fs> : 20 ?5 ;
< 20 fs> : 40 ?6 ;
< 20 fs> : 80 ?7 ;
end;
priority_encoder_2.pat
vasy -I vhd -Vao priority_encoder_2
asimut -b priority_encoder_2 priority_encoder_2 priority_encoder_out