Noting that I haven't used lots of high level blocks and integration, and don't know Verilog,

I was taught VHDL, and I fail to see what the big fuss is. Perhaps this is because my perspective is different.

When I was told that VHDL is a *descriptive language*, not a sequential programming language, I understood this. It seems like almost no one ever comes to understand this, to see how (static, combinatorial) logic might be (literally) "spelled out".

Moreover, synthesizers use a very small subset of VHDL; while a real digital logic circuit is perfectly capable of implementing a "delay(10ns)" or what have you, a synthesizer never will; it must be implemented by clock edges instead (which means dramatically more trouble, as you probably have to mux between phases of a PLL -- assuming you have such equipment available -- a PLL being, at heart, an analog function provided by proprietary interface and synthesis, not even realizable in VHDL on its own).

When I write VHDL, I approach it entirely from the angle of RTL. What logic am I describing? It starts with a logic diagram, then the implementation follows, and the synthesizer output is checked for correctness (and device operation, and inevitable debug cycles..). When I talk VHDL with others, I find they regularly try to represent things as programmatical, which is fundamentally wrong; I always go directly to "what logic are you trying to synthesize?" -- and often get blank looks at an apparently alien approach!

Since synthesizers are restricted to a subset, and I'm only trying to describe RTL, writing VHDL is very easy. Direct (combinatorial) logic operations can be implemented in an architecture. Sequential (latch/register) operations can be implemented in a process. Both can be used together, or much of it can be grouped inside the process (it always bothered me that the available combinatorial "conditional"/mux statements/blocks differ for the two areas). Or you can implement the freaking latches/flip-flops in 'bare metal' so to speak, but don't be surprised if the synthesizer (despite its vast compilational power) doesn't understand that you meant a regular latch, and you end up getting exactly the chain of gates you wrote, with subsequent poor performance. (But such is sometimes necessary, e.g. if you need to implement a dual clocked flip-flop. It's very easy to describe such a component in legitimate VHDL, but again, no synthesizer will make it for you.)

Tim