Vias for BGA 0.8mm pitch

[luiHS]

Hello
I have some designs with a RT1064 BGA microcontroller with a 0.8mm pitch.

The thing is that by using 0.2mm vias the PCB is more expensive than if they were 0.3mm, but I'm not sure if it would be correct to use 0.3mm vias with a hole with an external diameter of 0.45mm.

The vias I have installed now are 0.2mm holes with an external diameter of 0.45mm. If I increase the hole to 0.3mm while keeping the external diameter at 0.45mm, the ring that remains is thinner and I don't know if it can cause problems.

I am attaching images of both via configurations.

[uer166]

0.2 is probably the way. You don't want the annular ring to be so small and have a need for such good registration between drill and PCB. 0.2mm isn't thAt much more expensive anyway

[luiHS]

Thanks, I finally asked JLCPCB and they told me that if the via diameter is not greater than 0.45mm I can have the drill at 0.2mm at no extra cost.

What also happened is that I had the automatic calculation of the via diameter wrongly configured and for 0.2mm drills they set them to 0.4mm in diameter and that does have an extra cost. I also had the via diameter calculation wrongly configured for the internal layers on a 4-layer board, and some came out at 0.45mm and others at 0.40mm

[glenenglish]

I use 0.45/ 0.2 with JLC for 0.8mm BGA..... no issue, but usually I use 1.2mm thick up to 8 layers which reduces aspct ratio related limits and yield issues

[asmi]

Also, if you're designing 6 or more layer PCB with JLCPCB, I highly recommend using VIPPO.

[bson]

Note that JLCPCB plugs vias unless asked not to, making via in pad work just fine.  At least for 4L+ boards.

[ali_asadzadeh]

you can use 0.25mm with 0.45mm ring too

[SiliconWizard]

Does JLCPCB support blind & buried vias for they 6+ layer PCBs?

[SiliconWizard]

Note that JLCPCB plugs vias unless asked not to, making via in pad work just fine.  At least for 4L+ boards.

They plug vias but with some resin. It's not conductive. So that's ok for larger pads (plugging this way will avoid vias to suck solder in) but can't be used for small pads like for BGAs, for which you need true VIP (which is plated over, VIPPO), which is available only for 6+ layers at JLCPCB and at a significant added cost. I've read somewhere that JLCPCB currently supposedly offers that at no extra charge, but using the online quote, it *is* definitely an extra charge (about $300 extra for a small 6-layer board in small quantities).

[Tobias89]

Considering the ball size of 0.3 mm diameter approximately, it's perfectly fine to use 0.3mm hole via with 0.6 mm external diameter.

If you want to avoid via in pad, just offset them and you'll be fine (I've been doing this for the past couple of years).
Here is an illustration:


Depending on the number of signals you want to fan out, you'll maybe need blind/burried vias.. But if you are OK with TH vias, this is the way I recommend.

[asmi]

Does JLCPCB support blind & buried vias for they 6+ layer PCBs?

Unfortunately no.

[asmi]

They plug vias but with some resin. It's not conductive. So that's ok for larger pads (plugging this way will avoid vias to suck solder in) but can't be used for small pads like for BGAs, for which you need true VIP (which is plated over, VIPPO), which is available only for 6+ layers at JLCPCB and at a significant added cost. I've read somewhere that JLCPCB currently supposedly offers that at no extra charge, but using the online quote, it *is* definitely an extra charge (about $300 extra for a small 6-layer board in small quantities).

VIPPO can be done with both conductive and non-conductive filling. The latter is offered for free for 6+ layer PCBs (and I've used it many times and it's great! I even posted some photos of such boards here), if you absolutely need conductive filling, then it's going to be expensive upcharge.

[luiHS]

Considering the ball size of 0.3 mm diameter approximately, it's perfectly fine to use 0.3mm hole via with 0.6 mm external diameter.

If you want to avoid via in pad, just offset them and you'll be fine (I've been doing this for the past couple of years).
Here is an illustration:
(Attachment Link)

Depending on the number of signals you want to fan out, you'll maybe need blind/burried vias.. But if you are OK with TH vias, this is the way I recommend.

How many layers for this routing? It seems like 6 layers for a 289-ball MCU.

Is it possible with 4 layers for a 196-ball microcontroller like the RT1064, to route all the balls? Using normal vias so as not to increase the cost of the PCB.

[bson]

Note that JLCPCB plugs vias unless asked not to, making via in pad work just fine.  At least for 4L+ boards.

They plug vias but with some resin. It's not conductive. So that's ok for larger pads (plugging this way will avoid vias to suck solder in) but can't be used for small pads like for BGAs, for which you need true VIP (which is plated over, VIPPO), which is available only for 6+ layers at JLCPCB and at a significant added cost. I've read somewhere that JLCPCB currently supposedly offers that at no extra charge, but using the online quote, it *is* definitely an extra charge (about $300 extra for a small 6-layer board in small quantities).

They plate it with copper after plugging.  It's not entirely clear, but I read the following to say for < 6-layer boards they use epoxy, and for 6+ they default to copper paste (= conductive).

"Vias are filled with epoxy resin or copper paste and then plated over to achieve an opaque and smooth finish.
Click for detailed explanation

① Vias are filled and plated over. Choose copper paste filling for applications requiring high thermal conductivity.

② This process is the default for 6-layer and above multilayer boards.

③ Compatible with via diameters from 0.15 to 0.5 mm."

Here are the additional details:
https://jlcpcb.com/help/article/pcb-via-covering

It seems the main reason to use copper paste would be for thermal conductivity.

But either way, with resin plugging and copper plating for exposed copper (pads) it should be perfectly find to use via-in-pad for BGAs.  Assuming the via is small enough, of course.

[SiliconWizard]

Does it sound at all possible to have them manufacture a PCB for BGAs with 0.4mm pitch?

[asmi]

Does it sound at all possible to have them manufacture a PCB for BGAs with 0.4mm pitch?

Not with VIPPO, as according to this article https://jlcpcb.com/blog/Free-Via-in-Pad-on-6-20-Layer-PCBs-with-POFV the minimum drill for them is 0.2 mm, and pad diameter is 0.3 mm. Which is obviously too large for 0.4 mm pitch BGA. Now, in another place they write that 0.15 mm drills are also supported for VIPPO, which will theoretically yield pad size of 0.25 mm, which is closer to what 0.4 mm require.
I personally used their VIPPO process with 0.2-0.25-0.3 mm vias, and results we great.

[asmi]

They plate it with copper after plugging.  It's not entirely clear, but I read the following to say for < 6-layer boards they use epoxy, and for 6+ they default to copper paste (= conductive).

That's not been my experience. They use epoxy by default for free for 6+ layer PCBs (infact they automatically switch this option on in their quote form), but conductive filling is still a paid option.

It seems the main reason to use copper paste would be for thermal conductivity.

Yep, but it's too expensive to be practical in all but the most demanding cases.

But either way, with resin plugging and copper plating for exposed copper (pads) it should be perfectly find to use via-in-pad for BGAs.  Assuming the via is small enough, of course.

Yep, this is how I used them (and also inside thermal pads of QFNs).

[SiliconWizard]

Does it sound at all possible to have them manufacture a PCB for BGAs with 0.4mm pitch?

Not with VIPPO, as according to this article https://jlcpcb.com/blog/Free-Via-in-Pad-on-6-20-Layer-PCBs-with-POFV the minimum drill for them is 0.2 mm, and pad diameter is 0.3 mm. Which is obviously too large for 0.4 mm pitch BGA. Now, in another place they write that 0.15 mm drills are also supported for VIPPO, which will theoretically yield pad size of 0.25 mm, which is closer to what 0.4 mm require.
I personally used their VIPPO process with 0.2-0.25-0.3 mm vias, and results we great.

According to their "high precision PCB" quote page, 0.15/0.25 vias should be fine, but it's an option with added cost compared to 0.2/0.3. Still, they prefer 0.15/0.3, so not clear what their decision factor is. I guess it may depend on your overall design and how copper is distributed to avoid under/over etching. With their "copper paste filled & capped" option, which I'm pretty sure would be mandatory for such a PCB, the added cost makes JLCPCB not as attractive as with more basic options compared to its competitors.

Would be cool if they had a feature on their website where you could submit Gerbers and it would give you their recommended minimum options and DRC results, without having to submit an order.

[asmi]

According to their "high precision PCB" quote page, 0.15/0.25 vias should be fine, but it's an option with added cost compared to 0.2/0.3. Still, they prefer 0.15/0.3, so not clear what their decision factor is. I guess it may depend on your overall design and how copper is distributed to avoid under/over etching. With their "copper paste filled & capped" option, which I'm pretty sure would be mandatory for such a PCB, the added cost makes JLCPCB not as attractive as with more basic options compared to its competitors.

The problem is that even if they will be able to manufacture 0.15/0.25 mm VIPPOs, you still won't be able to fit a trace between such vias placed on 0.4 mm grid (0.08 mm trace requires at least 0.08 * 3 = 0.24 mm, while 0.25 mm vias only leave you 0.15 mm). So you can only use very limited subset of such BGAs with signals no further than 2 layers deep. That is, unless you want to play this game with removing internal annular rings to provide just enough space for a trace.

[SiliconWizard]

That's what they suggest: https://jlcpcb.com/help/article/BGA-Design-Guidelines---PCB-Layout-Recommendations-for-BGA-packages

[bson]

Would be cool if they had a feature on their website where you could submit Gerbers and it would give you their recommended minimum options and DRC results, without having to submit an order.

Yes!!!

And also, getting a quote to price out options before even starting a layout, before anything resembling a gerber exists to begin with.

[langwadt]

According to their "high precision PCB" quote page, 0.15/0.25 vias should be fine, but it's an option with added cost compared to 0.2/0.3. Still, they prefer 0.15/0.3, so not clear what their decision factor is. I guess it may depend on your overall design and how copper is distributed to avoid under/over etching. With their "copper paste filled & capped" option, which I'm pretty sure would be mandatory for such a PCB, the added cost makes JLCPCB not as attractive as with more basic options compared to its competitors.

The problem is that even if they will be able to manufacture 0.15/0.25 mm VIPPOs, you still won't be able to fit a trace between such vias placed on 0.4 mm grid (0.08 mm trace requires at least 0.08 * 3 = 0.24 mm, while 0.25 mm vias only leave you 0.15 mm). So you can only use very limited subset of such BGAs with signals no further than 2 layers deep. That is, unless you want to play this game with removing internal annular rings to provide just enough space for a trace.

afaiu some manufacturer will automatically remove unconnected internal annular rings no matter what and claim it gets higher yield

[asmi]

And also, getting a quote to price out options before even starting a layout, before anything resembling a gerber exists to begin with.

You can do it right now using their quote form. I do it all the time during PCB planning, as you can play around with different parameters to see if price difference would be justified by some other advantages. For example, for 10 layer boards 0.25 mm via and 0.2 mm via options were very close price-wise, so I went for 0.2 mm out of convenience, same thing about layer count - sometimes adding 2 additional layers make routing so much easier that this reduction of routing time offsets a relatively minor increase in price. I became a father recently, which drastically cut down on my spare time, so now that difference for a hobby project could mean if project gets completed at all or not, as I just can't devote as much time for it as I used to in the past.

[Tobias89]

How many layers for this routing? It seems like 6 layers for a 289-ball MCU.

Is it possible with 4 layers for a 196-ball microcontroller like the RT1064, to route all the balls? Using normal vias so as not to increase the cost of the PCB.

This is a 6-layer fanout, but the electrical clearance used is very conservative (0.15mm / 6 mils). You can optimize the layer count if you use 4 mils.

4 layers and normal vias doesn't seem possible to me. Either use a blind/burried vias or smaller clearance. If not both.

[luiHS]

This is a 6-layer fanout, but the electrical clearance used is very conservative (0.15mm / 6 mils). You can optimize the layer count if you use 4 mils.

4 layers and normal vias doesn't seem possible to me. Either use a blind/burried vias or smaller clearance. If not both.

Ok, I understand.
Could we say that in a BGA up to the fourth row of balls we can get tracks with conventional vias and 4 layers, and beyond the fourth row it becomes complicated using only 4 layers?.

So far I have not needed to get so many tracks from a BGA, but I have a project with an STM32 and an SDRAM memory that may need many ports, the version I made was with LQFP from an STM32H747, but I would like to do it with a BGA.