Author Topic: Beginning CPLD/FPGA xxx times PWM - resources  (Read 1814 times)

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Offline glatocha

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Beginning CPLD/FPGA xxx times PWM - resources
« on: May 25, 2013, 03:27:29 am »

I am on the beginning of learning PLDs. I have a CoolRunnerII Development Board, so will focus on Xilinx.
I thought that having an product idea will help to drive me through the learning process.

So the idea is - Multi RGB LED controller
Input from the MCU -> shift registers store the value -> comparators compare with timer -> result stream out by serial interface to LED Controller.

So my question is. How many resources (makrocells) of CPLD this design will use. Can I put in (let's say 256 makrocells still reasonable package) 100 PWM channels? Or maybe 1000?

How to do such assumptions?


Offline TerminalJack505

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Re: Beginning CPLD/FPGA xxx times PWM - resources
« Reply #1 on: May 25, 2013, 04:36:57 am »
The easiest way that I know of to 'ballpark' the macrocell count is to count the number of registered bits you are going to need.  That will be the absolute minimum number of macrocells you will need since there is only one register per macrocell.

So, for example, an 8-bit timer will take a minimum of 8 macrocells and each of the 8-bit registers will need 8 macrocells and so on.

Offline mikeselectricstuff

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Re: Beginning CPLD/FPGA xxx times PWM - resources
« Reply #2 on: May 25, 2013, 08:35:57 am »
CPLDs are  probably not an optimal choice cost-wise due to limited registers - a small FPGA would probably be better. If all you want is PWM, then there are several dedicated chips, many of which also do current regulation.
However as a learning exercise it's a fairly good choice - fairly simple to get going initially, then plenty of scope to explore different ways to implement to maximise efficiency.
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