Electronics > Microcontrollers
WCH $0.10 USD RISC-V MCU
jnk0le:
FYI
With a bit cursed github workflow, I've got someones GPL-lettered openocd fork to build windows binaries.
https://github.com/jnk0le/openocd-wch/releases/tag/29042023
v003 confirmed to work and open eclipse debug session.
No idea about the rest as I don't own those and cfg scripting is cursed similarly to code quality (even compared to extracts from MRS).
EDIT: it turns out that it requires proprietary drivers to work (enumerate as WCH-LinkRV instead of WCH-Link). Zadig WinUSB doesn't work.
jnk0le:
some notes after briefly debugging this thing:
- debugger cannot step over `ebreak` instructions (single step as well as "continue" option). However eclipse breakpoints do work. Probably something with openocd code.
- MIE csr register is non functional
- `mie` bit can be written (high) by csr instructions only when it's written together with `mpie` (must write 0x88 instead of 0x08).
Debugger can however write `mie` bit without touching `mpie`
- after a hard reset (remove power, short vcc to gnd), sometimes the `mpop` and `mppop` are set in `mstatus` register
- 0x744 in `ra` after hard reset (anyone else?)
jnk0le:
Finally got the startup code a bit more optimized than the vendor one.
https://github.com/jnk0le/simple-crt/tree/master/ch32v003
while(1) is 208 bytes with static initializers (194 without), and blinky (volatile delay) is 286 bytes.
ED: now it's 202, 188, and 280 bytes
HwAoRrDk:
--- Quote from: jnk0le on May 06, 2023, 06:19:49 pm ---- MIE csr register is non functional
--- End quote ---
That's because it doesn't have an MIE register (nor MIP). The list of supported CSR registers can be found in the WCH QingKeV2 CPU manual.
Interrupt enable/disable/status are controlled by the proprietary PFIC peripheral using the PFIC_* registers (I say 'proprietary', but it's basically a clone of the STM32F103's NVIC).
jnk0le:
--- Quote from: HwAoRrDk on May 07, 2023, 07:18:56 pm ---
Interrupt enable/disable/status are controlled by the proprietary PFIC peripheral using the PFIC_* registers (I say 'proprietary', but it's basically a clone of the STM32F103's NVIC).
--- End quote ---
Those are per interrupt ones somewhat redundant to the core `mie` in `mstatus`, and the ones inside peripherals.
Navigation
[0] Message Index
[#] Next page
[*] Previous page
Go to full version