Author Topic: Experience with ftdi fifo to USB 3.0  (Read 10284 times)

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Offline Howardlong

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Re: Experience with ftdi fifo to USB 3.0
« Reply #50 on: November 13, 2019, 08:16:45 am »
The point above concerning handshaking still puzzles me though. Could you give me an example of an MCU (it's not a trick or challenge question, but a real one) that has a parallel interface peripheral that can transparently handle handshaking (compatible with "empty" and "full" states of an external FIFO) in DMA mode? (Because if you have to handle those by polling, it'll make for pretty inefficient transfers IMO, as the DMA would not directly be usable).

The way I saw it working in the particular case I was looking at was to use a parallel port interface (50MT/s on the device I am targeting) or the external bus memory interface (66MT/s). These can be burst written from DMA. When the FIFO empties, it can be re-filled by a level change on a GPIO triggering an interrupt which restarts the DMA.

 

Offline SiliconWizard

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Re: Experience with ftdi fifo to USB 3.0
« Reply #51 on: November 13, 2019, 07:37:54 pm »
The point above concerning handshaking still puzzles me though. Could you give me an example of an MCU (it's not a trick or challenge question, but a real one) that has a parallel interface peripheral that can transparently handle handshaking (compatible with "empty" and "full" states of an external FIFO) in DMA mode? (Because if you have to handle those by polling, it'll make for pretty inefficient transfers IMO, as the DMA would not directly be usable).

The way I saw it working in the particular case I was looking at was to use a parallel port interface (50MT/s on the device I am targeting) or the external bus memory interface (66MT/s). These can be burst written from DMA. When the FIFO empties, it can be re-filled by a level change on a GPIO triggering an interrupt which restarts the DMA.

Unfortunately (unless again I miss something), the 'empty' and 'full' flags of the FT60x work as with most FIFOs: the TXE flag, for instance, for "TX empty" is a misnomer: it's just the negate of a "TX full" state: it basically indicates that you can write at least one word to the FIFO, not that it is actually completely empty...! So you can never know if you can write more than one word to the FIFO at each clock pulse... Now this is the same as with the FT232H/2232H series, but in the "245 synchronous mode". The FT60x also have a multi-channel mode that seems a bit more involved; I'll let you study the datasheet to figure out if what you want to do is possible in this mode, but I don't think it is in the former "245 synchronous" one.
 

Offline Howardlong

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Re: Experience with ftdi fifo to USB 3.0
« Reply #52 on: November 14, 2019, 05:13:20 pm »
Part of me wants to see if I can get an MCU <=> FT600 to work with a small single chip FPGA solution like a Lattice MachXO2 purely as an academic exercise. The other part of me knows it's never going to find its way into a commercial product though.
 

Offline SiliconWizard

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Re: Experience with ftdi fifo to USB 3.0
« Reply #53 on: November 14, 2019, 05:24:14 pm »
Meanwhile, have you looked at the Cypress GX3? It's apparently (found it on Arrow) much cheaper than the FX3 (~10€), which is a fair price for an MCU+USB SS+ Gigabit Ethernet all integrated IMO.
 

Offline PCB.Wiz

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Re: Experience with ftdi fifo to USB 3.0
« Reply #54 on: November 14, 2019, 07:08:54 pm »
Part of me wants to see if I can get an MCU <=> FT600 to work with a small single chip FPGA solution like a Lattice MachXO2 purely as an academic exercise. The other part of me knows it's never going to find its way into a commercial product though.
Why not ? The simpler FPGAs are being pushed as camera bridges, and this is not too different to that ?
The Lattice iCE40 UltraPlus is small && has large memory too, so maybe that can manage whole packets - less clear is what peak-speed it can manage
 


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