Electronics > Microcontrollers

What main gotchas are there going STM32F4xx to STM32H7xx

(1/8) > >>

peter-h:
My project is done on the 32F417 and I see no immediate need to go to the H7, but it does seem to be a way to get a longer product life, as well as getting about 3x more speed.

Looking back over the last few years I recall many gotchas, mainly related to different caching mechanisms. For example


--- Code: ---{
 __asm volatile( "dsb" ::: "memory" );
 __asm volatile( "wfi" );
 __asm volatile( "isb" );
}
--- End code ---

Above is from the FreeRTOS port but IIRC DSB doesn't do anything on the 32F4. Then in the ETH low level I see


--- Code: --- /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
 //__DMB();
 heth->TxDesc->Status |= ETH_DMATXDESC_OWN;
 /* point to next descriptor */
 //__DMB();
 heth->TxDesc = (ETH_DMADescTypeDef *)(heth->TxDesc->Buffer2NextDescAddr);
--- End code ---

where the DMB also does nothing hence is commented-out. But few people seem to really know... Some here: https://community.st.com/s/question/0D73W000001PMYnSAO

I am not planning on doing anything radical like zero-copy ETH/LWIP, which incidentally (for the H7)  I believe is the only 32x code that somebody spent a lot of time on fixing the bugs.

Other things I recall are not going to break code e.g. some H7 chips can do DMA to the CCM, which is nice.

What is news to me is this on the STM website

The STM32H7 single-core and value lines are pin-to-pin compatible with the STM32F7 series and STM32F4 series for the most common packages.

I wonder which chips that is true for?

AndyC_772:
The need for ISB / DSB instructions is an important one you've already spotted.

Some areas of memory are cacheable, and some aren't. Maintaining cache coherency is up to you. If you use DMA, it's best to use tightly coupled memory, which isn't cached but does run at full speed IIRC.

Do check the difference in power consumption - H7 gets warm, F4 doesn't to any great degree.

gpr:

--- Quote from: AndyC_772 on September 17, 2024, 07:09:55 pm ---If you use DMA, it's best to use tightly coupled memory, which isn't cached but does run at full speed IIRC.

--- End quote ---
Be careful with that, DTCM doesn't work with DMA, at least on some models of H7. Refer to documentation if unsure.

rhodges:
In some thread about cache coherency, I said that MIPS was fun. But that was really sarcastic. Keeping coherency between the cached memory and physical memory needed attention in the device drivers. I have worked with STM32, but not with the advanced cache devices. I suggest care with physical and cached memory.

peter-h:

--- Quote ---H7 gets warm, F4 doesn't to any great degree
--- End quote ---

I am seeing CPU temp +47C with Tamb of +20C, running fairly normal sort of code, RTOS, context here:
https://www.eevblog.com/forum/microcontrollers/freertos-where-should-the-cpu-be-spending-most-of-its-time/msg4965922/#msg4965922
I looked at the H7 specs and it is about 2x the power at 480MHz versus 168MHz for the 32F4.


--- Quote ---Keeping coherency between the cached memory and physical memory needed attention in the device drivers. I have worked with STM32, but not with the advanced cache devices. I suggest care with physical and cached memory.
--- End quote ---

This seems to be the biggest concern but what kind of code would bite you? One obvious one is moving data using code, with the data being put in RAM by DMA - as in ETH low level code. But looking at the above stuff I posted it seems more subtle.

Navigation

[0] Message Index

[#] Next page