From the wording of your post "knowledge in JTAG test", I would imagine they are meaning boundary-scan rather than classic MCU debug (i may be wrong of course, but it would seem silly to specify JTAG in reference to MCU debug)
The problem with boundary-scan is it can get very complex very quickly. In order to manipulate signals on the board, you need to clock through pretty large arrays of bits to set IO pins and read back statuses (imagine a huge shift register controlling the IO pins). Its an insanely useful tool for complex boards with interconnected FPGAs, memories and micros etc (assuming all are boundary-scan capable), by manipulating the IO pins via the boundary scan registers and clocking the resulting statuses back out, you can test continuity between pins, check for shorts and even do functional tests on SPI ADCs for example.
But, the fun part is, that can be a hugely complex task to handle without some kind of abstraction layer. At first glance, I can't quite work out how the OpenOCD stuff supports boundary scan, I presume it's a basic "provide it with a test vector and it clocks back out the resulting statuses of the pins". Many companies often use some proprietary software like XJTAG or Corelis which provides a nice schematic netlist comprehension, automation of continuity checks and abstraction layers to emulate SPI protocols etc... but those tools are expensive... very very expensive.
The OpenOCD looks promising and it would certainly be a valid learning exercise to get to grips with how you can impliment a useful boundary-scan test on such a low level, I'm sure there's even a reasonably priced dev-board with a boundary-scan capable MCU (low-end micros tend not to have boundary scan) or CPLD/FPGA.
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