Author Topic: What's happening in the world of MIPS?  (Read 3584 times)

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Offline Whales

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What's happening in the world of MIPS?
« on: October 12, 2018, 02:21:49 pm »
Traditionally I've seen MIPS have a stronghold in the consumer router market, mainly through Broadcom.  I recall hearing a rumour about this being due to licensing costs being lower than ARM.  That and they don't really have to care about power consumption, the customer pays.

Now I'm seeing some home routers come out using ARM based chipsets, and I'm wondering is MIPS SoCs are losing their financial edge.

Q1: Are there any new MIPS chips coming out?
Q2: Who are still using them?  Any other stronghold markets?

Online NorthGuy

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Re: What's happening in the world of MIPS?
« Reply #1 on: October 12, 2018, 02:29:06 pm »
Microchip uses MIPS in PIC32. They bought Atmel, which used ARM in their MCU. I think they're about to drop their MIPS line and will rename Atmel SAM chips into PIC32.
 

Offline legacy

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Re: What's happening in the world of MIPS?
« Reply #2 on: October 12, 2018, 02:52:31 pm »
Probably future MIPS will be found only in Chinese products based on the successors of the Dragon chip. And they will be MIPS64-LE.
 

Offline kfnight

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Re: What's happening in the world of MIPS?
« Reply #3 on: October 12, 2018, 02:54:06 pm »
It lives on in RISC-V.
 

Offline legacy

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Re: What's happening in the world of MIPS?
« Reply #4 on: October 12, 2018, 03:15:06 pm »
It lives on in RISC-V.

and in our computer science's books  :D
 

Online SiliconWizard

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Re: What's happening in the world of MIPS?
« Reply #5 on: October 12, 2018, 03:35:54 pm »
I believe this has been discussed several times in other threads, so you may want to do a little searching in the forum which will avoid people repeating themselves endlessly. ;D

That said, this is some kinda recent news that could change matters completely for the future of MIPS:
https://www.mips.com/press/wave-computing-extends-ai-lead-by-targeting-edge-of-cloud-through-acquisition-of-mips/
 

Offline westfw

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Re: What's happening in the world of MIPS?
« Reply #6 on: October 13, 2018, 04:05:31 am »
I think MIPS has had happening what I am afraid will happen to ARM after the Softbank acquisition.   Probably some high management guru decided "enough with all this diversification, trying to be everything for everyone.   Focus exclusively on THIS "highly profitable" market segment (I think it was network appliances for MIPS.  It'd probably be phones for ARM.)  :-(It may sound good on paper, but it tends not to be what ends up providing innovation in CPU technology.


 

Offline Whales

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Re: What's happening in the world of MIPS?
« Reply #7 on: October 13, 2018, 07:41:03 am »
Quote
Microchip uses MIPS in PIC32. They bought Atmel, which used ARM in their MCU. I think they're about to drop their MIPS line and will rename Atmel SAM chips into PIC32.

I had no idea those were MIPS, I presumed they were their own fancy arch.  Thanks.

It lives on in RISC-V.

Does RISC-V use a lot of MIPSy content, or do you mean spiritually?

Quote
I believe this has been discussed several times in other threads, so you may want to do a little searching in the forum which will avoid people repeating themselves endlessly. ;D

Hey, are you trying to tell me you prefer RETs over JMP loops? 

I'll have a hunt :)

Offline Whales

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Re: What's happening in the world of MIPS?
« Reply #8 on: October 13, 2018, 08:15:21 am »

Offline technix

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Re: What's happening in the world of MIPS?
« Reply #9 on: October 13, 2018, 09:05:00 am »
I think MIPS has had happening what I am afraid will happen to ARM after the Softbank acquisition.   Probably some high management guru decided "enough with all this diversification, trying to be everything for everyone.   Focus exclusively on THIS "highly profitable" market segment (I think it was network appliances for MIPS.  It'd probably be phones for ARM.)  :-(It may sound good on paper, but it tends not to be what ends up providing innovation in CPU technology.
For ARM both the phones and microcontroller markets are at least equally profitable. A good portion of the world’s CPU supply last year is Cortex-M. The Cortex-R line might see the axe drop, as those chips feature-overlap Cortex-M, and it won’t be too hard to port lockstep to Cortex-M33F or Cortex-M4F.

As of MIPS, the problem is that people has realized that Cortex-A is as good in routing IP packets as MIPS, especially with the recent push by various vendors to build server-centric Cortex-A chips; meanwhile the talents accumulated in developing smartphone software is easily transferable. This enabled Cortex-A to encroach on the market segment previously dominated by MIPS.

As an practical example, the ATSAMA5D36 chip has two Ethernet interfaces. Connect the RMII to a PHY and RGMII to an Gigabit Ethernet Switch chip like RTL8367, add 128MB DDR2 and 16GB eMMC and you get a reasonable and highly expandable router.
 

Offline brucehoult

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Re: What's happening in the world of MIPS?
« Reply #10 on: October 13, 2018, 09:38:14 am »
It lives on in RISC-V.

Does RISC-V use a lot of MIPSy content, or do you mean spiritually?

RISC-V assembly language is very close to MIPS assembly language. The binary encodings are completely different.

RISC-V rearranged the instruction encoding to:

  • provide a huge amount of room for future extensions, even within the standard 32 bit opcode format
  • provide uniform support for versions with 32, 64 and 128 bit integer registers
  • provide integrated support for optional 16 bit opcodes (like Thumb2) and for 48, 64, 80 ... 192 bit opcodes for future extensions. You can tell the length of an instruction by examining the low-order bits of the first byte: 00/01/10 for 16 bit 00011-11011 for 32 bit, 011111 for 48 bit, 0111111 for 64 bit, nnnXXXXX1111111 for 80+n*16 bit (the XXXXX is for the register to put the instruction result in

All this was achieved, basically, by shortening the field for immediate constants, load/store offsets, and conditional branch offsets from 16 bits to 12 bits. To compensate, the field for LUI and AUIPC is increased from 16 to 20 bits so you can still load any 32 bit constant or refer to anywhere in a 32 bit address space (absolute or PC relative) with two instructions. Unconditional branches also have a 20 bit offset.

The downside is literals and offsets between +/-2k and +/-32k need two instructions instead of one in MIPS. If you use things like the standard "LI" pseudo-instruction then this is transparent.

As well as this, in RISC-V you can compare two registers for EQ/NE/LT/GE and branch in a single instruction (recent MIPS has this too), and load and branch delay slots were removed.

For anyone who knows MIPS it's very very familiar, just improved. And free for anyone to use.

In May, MIPS announced a new 32 bit chip with a new "NanoMIPS" encoding that has 16, 32 and 48 bit opcodes. That looks pretty good too, but it's proprietary as hell and late to the party.
« Last Edit: October 13, 2018, 09:40:18 am by brucehoult »
 

Offline legacy

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Re: What's happening in the world of MIPS?
« Reply #11 on: October 13, 2018, 11:33:12 am »
load and branch delay slots were removed.

even in m88k, but at the cost of a bubble in the pipeline.
do you know how is it implemented in RISC-V?  :-//
 

Online NorthGuy

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Re: What's happening in the world of MIPS?
« Reply #12 on: October 13, 2018, 01:49:31 pm »
and load and branch delay slots were removed.

The delay slot is a good thing. The cycle is lost anyway. Why not to execute an instruction?
 

Online andersm

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Re: What's happening in the world of MIPS?
« Reply #13 on: October 13, 2018, 02:15:59 pm »
The delay slot is a good thing. The cycle is lost anyway. Why not to execute an instruction?
It's an exposed pipeline implementation detail, which makes high-performance implementations more difficult. On the software side it also complicates exception handlers and debuggers.

Offline legacy

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Re: What's happening in the world of MIPS?
« Reply #14 on: October 13, 2018, 02:37:59 pm »
and load and branch delay slots were removed.

The delay slot is a good thing. The cycle is lost anyway. Why not to execute an instruction?

for several reasons, starting from the fact that it usually drives your crazy with hw-debuggers and ICEs.
You can handle it, in theory, but at the end of the day, it's ... annoying.

edit:
for the record, it's what makes the use of SPIM (MIPS-R2K PC-simulator) very comfortable in computer science classrooms and laboratories, and it's *the* reason why Motorola put a bit in the configuration register of their m88K in order to disable the delayed slot. It has been appreciated by everyone has ever needed to use an ICE.
« Last Edit: October 13, 2018, 02:44:13 pm by legacy »
 

Offline nctnico

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Re: What's happening in the world of MIPS?
« Reply #15 on: October 13, 2018, 03:02:44 pm »
and load and branch delay slots were removed.
The delay slot is a good thing. The cycle is lost anyway. Why not to execute an instruction?
for several reasons, starting from the fact that it usually drives your crazy with hw-debuggers and ICEs.
You can handle it, in theory, but at the end of the day, it's ... annoying.
I totally agree. The delay slot cures your lust to program MIPS assembly quickly.
There are small lies, big lies and then there is what is on the screen of your oscilloscope.
 

Online NorthGuy

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Re: What's happening in the world of MIPS?
« Reply #16 on: October 13, 2018, 03:50:03 pm »
I totally agree. The delay slot cures your lust to program MIPS assembly quickly.

You can always put "nop" into the delay slot if you don't like it. However you often can find something better than "nop" for the delay slot.

MIPS architecture is very good for C compiler. Therefore, using assembler doesn't give you much advantage over C on MIPS. Regardless, the vast majority of users write in C/C++ and most of them know nothing about delay slots. The complier, though, behind their back, can utilize the delay slots to increase performance.
 

Offline legacy

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Re: What's happening in the world of MIPS?
« Reply #17 on: October 13, 2018, 04:35:10 pm »
You can always put "nop" into the delay slot if you don't like it. However you often can find something better than "nop" for the delay slot.

emmmm  :palm: :palm: :palm:
 
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Offline brucehoult

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Re: What's happening in the world of MIPS?
« Reply #18 on: October 14, 2018, 12:03:51 am »
load and branch delay slots were removed.

even in m88k, but at the cost of a bubble in the pipeline.
do you know how is it implemented in RISC-V?  :-//

RISC-V is an instruction set. There are already dozens of different implementations at varying levels of performance, so they don't do things the same way.
 

Offline brucehoult

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Re: What's happening in the world of MIPS?
« Reply #19 on: October 14, 2018, 12:22:50 am »
and load and branch delay slots were removed.

The delay slot is a good thing. The cycle is lost anyway. Why not to execute an instruction?

The cycle may or may not be lost. On a simple implementation at low clock rate with only SRAM the result of a load might well be available to the next instruction. On a more complex implementation with scoreboarding or reservation stations etc the load might take several (or even many) clock cycles and the instruction using its result is put aside until the result is ready. This has been common in the x86 world since at least the Pentium Pro in 1995. On intermediate implementations the load might take several clock cycles (even from SRAM or cache) and if the result is needed by the immediately following instruction then the pipeline stalls -- in this case yes it's a good idea to put another instruction (or more) between the load and the use, if one is available.

Thee problem with delay slots baked into the instruction set (and you have to put a NOP there if you don't have anything more useful to do) is that they assume one particular implementation point -- probably the first one you do -- while being totally inappropriate for both higher end and lower end implementations later on.

As for branch delay slots, they have been made obsolete for 99% of branches by modern branch prediction techniques, even on microcontrollers such as the SiFive E31 (in the HiFive1) and E51. One those CPUs when the prediction is wrong you get to eat 3 clock cycles of stall, but it doesn't happen often. On the very low end E20/E21 (Cortex M0 competitor) there is no branch prediction and taken branches simply take 2 clock cycles. But you get compare-and-branch in one instruction.
 
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Online Marco

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Re: What's happening in the world of MIPS?
« Reply #20 on: October 14, 2018, 01:47:09 am »
On DSP loops anything but data based branch prediction always gets it wrong once every loop.
 

Online NorthGuy

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Re: What's happening in the world of MIPS?
« Reply #21 on: October 14, 2018, 02:11:29 am »
As for branch delay slots, they have been made obsolete for 99% of branches by modern branch prediction techniques, even on microcontrollers such as the SiFive E31 (in the HiFive1) and E51. One those CPUs when the prediction is wrong you get to eat 3 clock cycles of stall, but it doesn't happen often. On the very low end E20/E21 (Cortex M0 competitor) there is no branch prediction and taken branches simply take 2 clock cycles. But you get compare-and-branch in one instruction.

I understand. Delay slots make sense only when you fetch instructions one by one. When you have "far" DDR3/DDR4 memory and a system of caches, the delay slot certainly doesn't help much. It may even be harmful, for example if it is located beyond the cache line boundary and would require fetching the whole new cache line. Thus, it has been removed from the low end systems simply for uniformity reasons. Makes sense.
 

Offline brucehoult

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Re: What's happening in the world of MIPS?
« Reply #22 on: October 14, 2018, 03:17:33 am »
On DSP loops anything but data based branch prediction always gets it wrong once every loop.

Aren't most DSP loops controlled by a counter (e.g. array size) not by the data?
 

Offline westfw

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Re: What's happening in the world of MIPS?
« Reply #23 on: October 14, 2018, 06:47:37 am »
Heh.  Look what showed up elsewhere...
 

Online coppice

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Re: What's happening in the world of MIPS?
« Reply #24 on: October 14, 2018, 11:42:22 am »
I think MIPS has had happening what I am afraid will happen to ARM after the Softbank acquisition.   Probably some high management guru decided "enough with all this diversification, trying to be everything for everyone.   Focus exclusively on THIS "highly profitable" market segment (I think it was network appliances for MIPS.  It'd probably be phones for ARM.)  :-(It may sound good on paper, but it tends not to be what ends up providing innovation in CPU technology.
When ARM were developing the M3 and M0, MIPS was trying hard to go head to head with them, as they knew they could only survive by broadening their appeal across the whole of the embedded space. A number of MCU vendors evaluated the MIPS small core options, and found they had some pretty good qualities. In the end only Microchip signed up.
 


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