Actual analog audio electronics stuff is way outside my experience, but as I've played with various Teensies quite a bit, and lurk and occasionally participate at the
PJRC forums, here is my understanding about the issue, with hopefully useful links and references.
You can use one or two CS42448 codecs (use the automotive -DQZ versions, as the chips tend to get a bit hot; they're available at e.g. Mouser for under 17€ apiece) with Teensy 4.1 using I2S in TDM mode (i.e. SAI1 and SAI2, in the i.MX RT1062 documentation). Each CS42448 chip provides three stereo inputs and four stereo outputs (6ch in, 8ch out) at 16 bits at 44.1kHz sample rate (per channel) or better, so with two you should be able to get 12ch input (6 stereo inputs) and 16ch output (8 stereo outputs) simultaneously using Teensy Audio Library (which supports TDM). Since Teensy USB is High Speed/480Mbit/s, USB bandwidth is not a problem, either: a single 32-bit 96kHz audio channel is ~ 3 MBit/s, so ~ 30 channels is less than 100 Mbit/s, which Teensy 4.x can do even with USB Serial, so no problem with USB Audio (using isochronous transfers). USB Audio also means that if correctly configured on the Teensy end, the built-in USB audio drivers are used in your OS; it is a separate USB type in Teensyduino.
Paul Stoffregen (author of Teensies) created
an example board for Teensy 3.5/3.6 in 2017, using a single I2S. He also has a
Hackaday.io project for dual interleaved CS42448. You do not need to interleave the two CS42448's on Teensy 4.1, though, because it has three I2S buses, two of which can be used for TDM.
Essentially, on each CS42448, you connect MCLK to Teensy MCLKn (pin 23 or 33); ADC_SCLK and DAC_SCLK to Teensy BCLKn (pin 21 or 4); ADC_LRCK and DAC_LRCK to Teensy LRCLKn (pin 20 or 3); DAC_SDIN1 to Teensy OUT1A/OUT2 (pin 7 or 2); and ADC_SDOUT1 to Teensy INn (pin 8 or 5). If you set the I2C address bits different on each CS42448, you can connect both to the same I2C port (SCL and SDA on pins 19,18 or 16,17 or 24,25). Note that in this configuration, Teensy does generate both sets of clocks (deriving them from the same master clock), so they should not drift; but they're essentially completely separate I2S devices.
(For exact sync, you could set the first I2S as asynchronous (generating the clocks), and the second I2S as asynchronous (using the clocks), connecting the MCLK, SCLK/BCLK, and LRCLK together, ensuring SAI2 uses the clocks generated by SAI1; and both CS42448s use the exact same clocks. But note that this is dangerous, because a software misconfiguration or even configuring SAI1/SAI2 in the wrong order, may cause Teensy to drive the two connected pins to different voltages at the same time, essentially shorting 3.3V to GND, which will burn one or both of those Teensy pins.)
Note that the above boards do not include any kind of analog filtering or output amplification. The
Cirrus Logic CS42448 datasheet (PDF) section 7.1 suggests analog input filters, and 7.2 output filters. See figures 2 and 3 for the safe analog output region; without any amplification, the load resistance must be at least 3 kOhm.
(It is also possible to isolate the CS42448 chips, so that they and the analog filters operate with ground not tied to the Teensy or host computer ground, which helps avoid ground loops (but not between the different audio grounds, i.e. between the inputs and/or outputs). I don't know how useful it would be, but it might make it easier to get a better signal-to-noise ratio and audio frontend circuits, or something like that.)