^All of these same mistakes are also made by people using top of the line, modern microcontrollers and professional IDE and compilers.
I don't have (nor want to have) a dog in this fight, but is it really driving the GPIB bus to spec, or is it driving it to "works on my bench today with 3 devices connected"?
"Works on my bench today" is perfectly sufficient for a lot of use cases (I'm sure we've all done it), but it's hard to argue that it's a full drop-in replacement.
It depends what GPIB specifications are. As long as Vih is being met with 0.4V of extra margin for noise immunity on the other end, it's fine, it meets spec, and it is not a hack... as far as the output side of things.
So it depends on the specs of GPIB. How long cable it is supposed to work across, what gauge/resistance of wiring is the minimum recommended, and possibly how many are supposed to be daisy chained. If that other stuff isn't well defined, then even 5V output will fail at some point.
Add the fact that the logic levels aren't symmetrical to begin with. There is only 0.8V margin on the low side. Even at 3.3V, there's nominal 1.3 margin on the high side. So 3.3V output might work just as well as 5V (if Vil is what is violated, first). I suppose it depends what is the output impedance of the driver high vs low, and what is the amount of current drain caused by the input pins on the bus when high signal vs low signal, if that is asymmetrical, and if you have enough inputs connected for that to even matter.
Input side is another story.
Probably most important thing to check is to see what STM32 considers digital low input. CMOS spec, I think it's 0.5V, which is less than 0.8V. It doesn't mean STM32 is that sloppy/insensitive, just that is could be and still meet CMOS compatability spec. So proper low for TTL, at 0.7V, might not be low enough for STM32. In practice, any given device usually have a smaller/tighter "indeterminate window" than what is allowed by the protocol. That transition of high and transition of low just has to be within the window of that protocol. So in a way, no, this isn't necessarily equivalent to a proper TTL level interface. That is not inherently guaranteed, anyhow, by simple virtue that STM is CMOS compatible. But if 0.8V is recognized by STM as digital input low, which is fairly likely, it will more than likely work fine all the way to most demanding of GPIB specs.
So it would be left to you to determine if your specific CMOS device actually meets TTL specification of ViL 0.8V or not.