Why do internal pullup resistor's have a range ?

[Siwastaja]

They have a high value, just switch on something with a large power or inductance nearby, and such a sensitive input will react.

Even larger external pull-up values are regularly used, e.g. in cases where low power consumption is important. I have used values close to 1Mohm. Sensitivity to external fields or conducted emissions depends on the whole design, including length of traces and layout plus other filtering components. The resistance values is just the tip of the iceberg.

If 50k-ish was a very poor value, manufacturers would not do it. Usual pull-up values seen in circuits vary between about 2k to 100kOhm, though.

[bson]

They're not resistors, but pairs of FETs biased into the ohmic region.  The channel resistance is highly dependent on the process used and processes for digital circuits are mainly focused on high switching speeds: minimal ohmic regions, and low capacitance.  So you kinda get what you get.

[MathWizard]

I'm sure there's fixed resistor's with under 5% tolerance in this MCU.

Just curious: Do you have any basis for that assumption?

I tend to agree with SiconWizard, It's quite possible / likely it is not a "real" resistor at all. If you want to be sure, then put a potentiometer on it, and draw a few different currents out of the pin. For a true resistor, the relation between voltage (drop) and current is lineair. If the current stays sort of constant when the voltage drop reaches a few volts, then you can be pretty sure it's a transistor (or combination of transistors).

No but reading some answers here, yeah I figured by now, 2024, that making 5% resistors in a chip, would be easy, and worth the effort. Of all the things in a MCU to worry about, I didn't think some 5% PU resistors, on a few pins, would factor into the cost.

[Kleinstein]

Aiming for 5% accuracy resistors could add quite some costs (may even need a different process or extra trim steps). One can usually get accurate resistor ratios, but not accurate absolute values. There are not that much improvements in this ascpect. The pull-up resistor is essentially the R_on of a tiny FET. With FETs it is normal to have quite some variations there.

There is essentially no need for more accurate pull-up resistors. So the +-50% range rating is OK for essentially all users. So it is not good, but good enough. The very few cases were a more accurate value is needed one has to use an external resistor.

[SiliconWizard]

- Resistors take die area.
- They would still require a transistor to switch them on/off - and one with a low enough RDSon in the whole operating range that it would not add significantly to the above resistors, otherwise it wouldn't add any benefit. So, "much" larger transistors.

So there you go, instead of one small transistor, you'd end up with die area taken by one resistor + one much larger transistor. All this for a questionable benefit in 90% of the use cases.
And likely a greater probability of messing up the design of the IO pads, you'd en up in the circle of the contractor that the RPi used for the RP2350.

[Siwastaja]

All this for a questionable benefit in 90% of the use cases.

Or 99.99%. Because if you really need 5% tolerance, then you also need a specific value, not just some 10k or 20k or 5k or whatever designer thinks is a good value.

So make that, say, 4 resistors with resistance 2^n for 16 software-configurable values, and 4 transistors to switch them. And then the same for pulldowns, of course. Probably still less than 5 cents per chip to do, but it's a slippery slope of features. There will always be limitations what microcontrollers can do so it makes no sense to try to do everything when it's easily achievable with small and cheap external component.

Better use that same budget to implement, say, CAN peripheral, because external SPI-to-CAN bridge is much more pain in the ass than external resistor. And 1-2% of customers might actually need CAN.

[hans]

In my master courses on CMOS design, we typically used +/-20% as the absolute accuracy of transconductance at room temperature.

So if they designed for a 40k pull-up (or a weak CMOS transistor to Vdd with Id set at e.g. 82.5uA @ 3.3V), then take +/-20% => 66-99uA range=> 33-50k range. Take voltage and temperature tolerance as well, and I'm certain a 20k-80k range is not unthinkable.

The point is that matching on-chip is quite good. If you take 2 separately fabricated FETs, both set them to the exact same drain current (as FETs are transconductors), then you'll likely have quite a big tolerance in gate voltage needed.
However, if you fabricate these 2 FETs on the same chip, very closely together, and with the proper structure/layout to balance any gradients in the doping across x/y directions, then it is possible to make an extremely well matched transistor pair. Their absolute specs can still be all over the place. But if you want to make a long tail circuit, that's usually not that important at all.
The PhD's I spoke to that were fully into analog (RF) CMOS design often said that schematic/simulation was about 10% of their work investment, and 90% was getting to a good layout that will work well across PVT.


The "old fashioned" way to accomplish this is to characterize each FET individually and then pair well matched parts together. It still needs to be done for exotic use cases, but fortunately you can still buy matched (J)FETs and the like which are inside a single package for a very good reason.

[bson]

CMOS of course is a complementary pair.  I think in any CMOS process the minimum cell is going to be at least a complementary pair - but I could be wrong.

[Doctorandus_P]

CMOS of course is a complementary pair.  I think in any CMOS process the minimum cell is going to be at least a complementary pair - but I could be wrong.

Yes, wrong. See: Gates get weird in the ALU



And on top of that, "CMOS" does not have to be strictly digital. Input can have current sources made from one FET. It's also getting more common to have analog circuits such as (de) multiplexers, comparators and even opamps integrated in microcontrollers, for example the STSPIN. ADC's and DAC's (also common in uC's) are also not strictly "digital". Overall, it's simply "whatever construction which gets the job done" and that is possible to make within the limits of the applied semiconductor technology, that will be implemented.

[Siwastaja]

"CMOS process" means a process optimized for producing P and N channel MOSFETs suitable to build complementary pairs. Of course process allows separately creating P and N channel transistors for things like open drain outputs. And analog stuff like opamps.