Cortex-m4 PLL Questions

[DrMag]

I'm in the middle of the EdX course that uses the Tiva C TM4C123 version of the Cortex-m4, and I'm a little befuddled by something with the PLL system. Hopefully someone can shed some light on my questions. 

1. The PLL is divided by anything from 1 to 128 for the system clock. (Datasheet says max frequency is 80 MHz, so presumably the first few of these are never used.) Most of these will be non-integer frequencies. In what situations might some choose a frequency of, say, 22.222 MHz (400/18) vs 20 MHz (400/20)? Is that even ever done in practice, or do most engineers default to an integer frequency?

2. The PLL output frequency can be set to either 400 MHz or 200 MHz. Why would this be put into the chip? I understand that you can attain lower frequencies out of the 200 MHz, but, presuming people typically default to integer values, that only adds 2 MHz to the mix. What benefits would be obtained by having both of these PLL values, rather than either just 400 MHz or 400 MHz and another value, say 300 MHz?

3. Because of the 1/n nature of the division, very few frequencies are available in the upper range. For the 400 MHz PLL, there are only 6 possible values between 40 and 80 MHz, while there are 11 between 20 and 40 MHz, and 109 between 2 and 20 MHz. This further compounds the confusion on the numerous selections of non-integer frequencies. I suppose there's no way around this particular quirk, but why not simplify the register to set only a handful of pre-determined divisors (those that give only integer frequencies, for example) rather than giving the option of having both 3.15 MHz and 3.125 MHz?

[xani]

1. The PLL is divided by anything from 1 to 128 for the system clock. (Datasheet says max frequency is 80 MHz, so presumably the first few of these are never used.) Most of these will be non-integer frequencies. In what situations might some choose a frequency of, say, 22.222 MHz (400/18) vs 20 MHz (400/20)? Is that even ever done in practice, or do most engineers default to an integer frequency?

some external devices require certain speed of clock. and some crystals are cheaper than others. Just adds flexibility in design

2. The PLL output frequency can be set to either 400 MHz or 200 MHz. Why would this be put into the chip? I understand that you can attain lower frequencies out of the 200 MHz, but, presuming people typically default to integer values, that only adds 2 MHz to the mix. What benefits would be obtained by having both of these PLL values, rather than either just 400 MHz or 400 MHz and another value, say 300 MHz?

I'm guessing it was just easy to put in so they added it. But yeah, doesnt sound that useful

3. Because of the 1/n nature of the division, very few frequencies are available in the upper range. For the 400 MHz PLL, there are only 6 possible values between 40 and 80 MHz, while there are 11 between 20 and 40 MHz, and 109 between 2 and 20 MHz. This further compounds the confusion on the numerous selections of non-integer frequencies. I suppose there's no way around this particular quirk, but why not simplify the register to set only a handful of pre-determined divisors (those that give only integer frequencies, for example) rather than giving the option of having both 3.15 MHz and 3.125 MHz?

You have a circuit that does stuff. You can either give user a register with all possible values and give them freedom to do whatever the hell they want with it (and things you wouldn't even think it could be used for) or you can use more transistors to limit user's ability to do stuff

[rsjsouza]

1. The PLL is divided by anything from 1 to 128 for the system clock. (Datasheet says max frequency is 80 MHz, so presumably the first few of these are never used.) Most of these will be non-integer frequencies. In what situations might some choose a frequency of, say, 22.222 MHz (400/18) vs 20 MHz (400/20)? Is that even ever done in practice, or do most engineers default to an integer frequency?

As mentioned before, in general the odd frequencies give flexibility if the developer wants to achieve a very specific performance versus power consumption tradeoff.
One detail that will influence your calculations, though: page 223 of the TM4C123 datasheet mentions the PLL is always divided by 2 - the tables on that page show the frequencies.

2. The PLL output frequency can be set to either 400 MHz or 200 MHz. Why would this be put into the chip? I understand that you can attain lower frequencies out of the 200 MHz, but, presuming people typically default to integer values, that only adds 2 MHz to the mix. What benefits would be obtained by having both of these PLL values, rather than either just 400 MHz or 400 MHz and another value, say 300 MHz?

Keep in mind that Cortex M4 cores can be scaled 200MHz+, therefore it is possible this high PLL was left there for future provisioning. The sister variant TM4C129, for example, runs at 120MHz.

3. Because of the 1/n nature of the division, very few frequencies are available in the upper range. For the 400 MHz PLL, there are only 6 possible values between 40 and 80 MHz, while there are 11 between 20 and 40 MHz, and 109 between 2 and 20 MHz. This further compounds the confusion on the numerous selections of non-integer frequencies. I suppose there's no way around this particular quirk, but why not simplify the register to set only a handful of pre-determined divisors (those that give only integer frequencies, for example) rather than giving the option of having both 3.15 MHz and 3.125 MHz?

Electronically speaking, dividing by factors of two is much less complex than implementing a Renard series.

[Sal Ammoniac]

A typical MCU has an internal and an external high-speed oscillator to generate the primary frequency reference. The HSI oscillator is typically implemented as a simple RC oscillator running at ~4MHz and is not very accurate. The HSE oscillator is usually driven by an external crystal or resonator and is much more accurate than the HSI oscillator.

Each MCU has limits to how fast the HSE oscillator can be driven. A typical upper limit is 25 MHz. To get to higher speeds, a PLL is used to generate higher frequencies. Configuring the PLL is probably the most confusing element of the whole clocking mechanism. It's really not too bad once you understand a few simple rules. The PLL has a component called a voltage controlled oscillator (VCO). This component of the PLL is responsible for the actual multiplication of the raw HSE (or HSI) clock. The VCO has a limit to the input frequency it can accept. It might be as low as 1 MHz. Since the HSE clock is usually higher than this, it's necessary to divide the HSE clock down to a value that fits into the VCO's input range. In general, you want to choose this divisor so as to put the input to the VCO near the top of its input range (to minimize jitter).

For example, let's say you have an 8 MHz crystal driving HSE and the PLL's VCO requires an input in the 1-2 MHz range. You would choose a divisor of 4 to divide the 8MHz HSE down to 2MHz, the upper limit of the VCO's input range.

Now it's necessary to choose a multiplier to multiply the VCO input up to a much higher clock rate. A typical VCO might be able to multiply its input by 2-400 times. Finally, there's usually a divider on the output of the PLL to bring the final clock frequency down to the range supported by the chip.

Continuing the previous example, we've divided the 8 MHz HSE clock generated by the crystal oscillator down to 2 MHz to match the input range of the PLL's VCO. Now we choose a multiplier of 168 to bring the VCO output up to 336 MHz. And finally choose a divider of 2 to bring the final clock output of the PLL down to 168 MHz, which is the maximum clock the MCU in this example supports.

The rest is just configuring the multiplexers to route the HSE clock signal to the PLL.

The total sequence typically goes like this:
1) Enable the HSE oscillator and wait for it to stabilize.
2) Configure the PLL.
3) Set the HSE as the input to the PLL.
4) Enable the PLL and wait for it to lock.
5) Switch the system clock to the output of the PLL.

Some MCUs have separate peripheral clocks that also need to be configured, but most of them are derived from the system clock with simple dividers.

Sometimes you want to use an odd system clock frequency. The most common reason for doing so is if you need to use a precise clock for a periphera,l such as a UART, so that you can get a baud rate that is error free.

[bingo600]

Remember to check if weird Xtals (clock) will support the onboard USB , that usually (ST) have a 48Mhz requirement (via pll magic)

/Bingo