[solved? i hope] spartan3e-500 sparkfun board, uncommon behavior on bootstrap

[legacy]

hi guys
i have bought this board
here it is the schematic

the onboard RS232-adapter is damaged (the TX is not working)



so i have removed all the jumpers (on the jp9 connector) which connect the maxim chip to fpga pins, and i wired to external RS232 adaptor (3.3V, 5V tolerant, powered by the fpga regulator at 3.3V).

i have put a 6809 SoC on bram (with SYSD9BUG v1.4 inside) and i have connect an uart cable to my PC

the problem is: it seems there is something which resets the SoC with cause uncommon behavior on the hyper terminal, i see this

Code: [Select]

SYSD9BUG v1.4 FOR S3E
> WHAT?
SYSD9BUG v1.4 FOR S3E
> WHAT?
SYSD9BUG v1.4 FOR S3E
> WHAT?
SYSD9BUG v1.4 FOR S3E
> WHAT?

that means that the SoC has been reseted several times


The same (VHDL) code has been synthesized for Digilent s3e-500-ug320 (instead of s3e-500-pg208 of the sparkfun board), and i see this on bootstrap

Code: [Select]

SYSD9BUG v1.4 FOR S3E
>


I checked the PowerSupply, 5V,1A, and it is low ripple, also the sparkfun has an onboard regulator that should filter residual noises on Vin


What could be wrong ?

should i investigate about the constraints, the hardware, the HDL ?

any suggestion is welcome 

[legacy]

any tips ?

[scientist]

get a new board? trying to work around broken circuits can be fun, but it isn't always successful.

[legacy]

the only broken part is the RS232 chip, the fpga has passed all the tests, including a very large SoC. The only issue i am experimenting is a strange behavior on bootstrap, once bootstrapped it works fine.

any suggestion about that ?

[scientist]

https://www.sparkfun.com/products/589

Just buy one of these and replace the one on your board. It's $1.95.

[legacy]

so i have removed all the jumpers (on the jp9 connector) which connect the maxim chip to fpga pins, and i wired to external RS232 adaptor (3.3V, 5V tolerant, powered by the fpga regulator at 3.3V).

i am fine with this external adaptor, the issue is not related to that

[scientist]

i would not be surprised if your reset issues are caused by having a different offboard chip.

[legacy]

it seems that today is the fix day

i have put my hot air station back in order to replace the RS232 damaged chip with a brand new one, all is well all ends well and the rx and tx are now working!

unfortunately i got the same issue about the strange behaviour at bootstrap, so i have put a an eye on the project constraints

i have replaced this

Code: [Select]

# Time specifications for 50MHz clock (soldered)
# (40%/60% duty-cycle)
#
NET "CLK_50MHZ"   LOC = "P181"

with this

Code: [Select]

# Time specifications for 50MHz clock (soldered)
# (40%/60% duty-cycle)
#
NET "CLK_50MHZ"   LOC = "P181" | IOSTANDARD = LVCMOS33 ;
NET "CLK_50MHZ" PERIOD = 20 ns HIGH 40 %;

i have also replaced the SYSD9BUG v1.4 firmware with a tiny and extremely easy piece of code that
- waits 200 cycles as early bootstrap
- resets the uart before any initialization
- does extremely paranoid built-in tests (such as address in address, cpu alu test, etc)
- reports everything with TEST(X):{PASSED, FAILED}

and ... i can't understand exactly why and where SYSD9BUG v1.4 has the uncommon behavior bootstrap issue, but according to these paranoid tests i can say the SoC is working on this fpga board because i have no TEST FAILED in my report screen.

my conclusion
(that my be wrong, inaccurate, etc, you have to consider i am not a fpga guru, i am just a fan)

- SYSD9BUG v1.4 has no issues on Digilent s3e-500-fg320 @50Mhz (soldered clock) board, with speedgrade -4 and poor constraints about clock

- SYSD9BUG v1.4 has issues on Sparkfun s3e-500-pq208 @50Mhz (soldered clock) board, speedgrade -4 and poor constraints about clock

- it seems that the Sparkfun s3e-500-pq208 board needs stronger constraints about clock

[legacy]

in my tests i am resetting the board several and several time, still no uncommon behavioral at the bootstrap

good 

next point is to understand why Noice09 is not working on both the boards, it should be fine with digilent s3e-500 but it is not working at all 

i think i will write the fw by myself, it should be not so complicate to add a sort of srec-to-memory, but, to be honest, i like the Noice09 PC side, it's a good piece of software which enables you to download and track an application.

ok 


thank you for the support 

[scientist]

great!