Mircro-controller designs to generate nano second pulses with variable delay.

[dmsc]

Hi!

Please see the attached image. I need 2 sets of pulses with variable delay between them i.e delay between (1,2) and (3,4) is can be fixed (50-100 ns) while I need to have control over the delay between the two sets.

This is exactly the application for the "one-pulse mode" of the STM32 timers, it is available in all the STM32 micros. From the reference manual:

One-pulse mode (OPM) is a particular case of the previous modes. It allows the counter to be started in response to a stimulus and to generate a pulse with a programmable length after a programmable delay.

By having the timer run at 20MHz (50ns period) you can get all the waveforms you sketched. You use one input and the 4 timer channels to generate each of the 4 outputs.

[radar_macgyver]

Similar timing waveforms are often encountered in radar applications, and are usually implemented in an FPGA or similar. One method I've found handy is to implement a programmable state machine with a block RAM to store the state transitions and the time delay to the next state transition. When the external trigger is received, the state machine starts from the beginning of the block RAM and 'plays back' the stored transitions. Resolutions of 10 ns are easy to achieve on older FPGA families, and 5 ns or shorter on newer ones. The waveform sequence may be easily changed by rewriting the block RAM contents.

One could also do a similar implementation using a memory block (SRAM, EPROM) and a counter.

[fracton]

I've been trying out a couple of microcontrollers and pulse-width modulator ICs suggested above in this thread. While I've explored using an FPGA to do they same job, for now it seems to be an overkill.

I will try to post results from some of tests with MCUs in this thread, soon.

[PCB.Wiz]

I've been trying out a couple of microcontrollers and pulse-width modulator ICs suggested above in this thread. While I've explored using an FPGA to do they same job, for now it seems to be an overkill.

I will try to post results from some of tests with MCUs in this thread, soon.

PWM controllers for motor drive are common these days, even in small MCUs, so you can almost manage a mostly hardware solution.
However, those work slightly differently from your pulses, in that they can trigger and produce a defined delay to a rising edge.

You can get 4 narrow pulses if you trigger 4 monostables, then you get fine analog control of the MOSFET pulse widths and the small MCU gives digital control of the times between pulses.

[mino-fm]

I will try to post results from some of tests with MCUs in this thread, soon.

You can use one PIO of RP2040. Define 4 outputs and shift out 32 bit patterns. If period is 12,5 ns each pulse will last 50 ns.

send to OSR-FIFO:
0x11110000   pulse 1 + 50 ns delay
0x00002222    50 ns delay + pulse 2

delay by sending 0x0 pattern, by counting down a register or missing of new pattern

send to OSR-FIFO
0x44440000   pulse 3 + 50 ns delay
0x00008888   50 ns delay + pulse 4

[PCB.Wiz]

Please see the attached image. I need 2 sets of pulses with variable delay between them i.e delay between (1,2) and (3,4) is can be fixed (50-100 ns) while I need to have control over the delay between the two sets.

Given that pulse scheme, that's not quite native PWM, but you can combine a two input gate driver neatly with a 2 setting PWM, for a no-additional parts solution.

eg looking at the RP2350 PICO



If PWM_A = IN- and PWM_B = IN +, the output is HI only in the difference region (B & !A)

I think the PICO can clock PWM to above 150MHz  giving set points for each edge, to drive 8 pins, for 4 gate drivers.
You can define any edge to 6.7ns granularity inside a 437us window (2^16).

Triggering is covered here

12.5.2.5. Level-sensitive and Edge-sensitive Triggering
The PWM provides the following counter modes:
• Default free-running, counting continuously whenever the slice is enabled (free-running)
• Count continuously when a high level is detected on the B pin (level sensitive)
• Count once with each rising edge detected on the B pin (rising edge-sensitive)
• Count once with each falling edge detected on the B pin (falling edge-sensitive)

[NorthGuy]

<100 ns, anything more than that would significantly increase the dead time of my device.

This is difficult for a CPU, so you'll need some logic. Some of the MCUs can do things automatically, such as trigger PWM or start timer using an external pulse, but even then they often have different synchronizers, so it might be over 100 ns by the time the signal is visible to the CPU. Such things are rarely documented, so you'll need to try.

Is there any way for you to anticipate the time when you need to start the pulse sequence? If you could send the trigger earlier, say 500 ns or 1 us before the sequence should start, this would remove the requirement for short latency, then practically any MCU will do.

Aside of the latency, everything else is trivial and can be done by practically any MCU.

[mino-fm]

Sitting here on a rainy day I liked to play around with RP2040 and Arduino. The result is shown as TO has given his demands. (Sorry for bad GND-connections.)
Using 200 MHz clock you get 5 ns timing which should be fine enough. As everyone knows RP2040 is working well at this frequency ;-)

Spacing between pulse_AB and pulse_CD can be modified by Serial Monitor of Arduino IDE or using a terminal programm.

[gdr771]

Whatever microcontroller you end up using, be sure to check if it has a switchable slew-rate limiting feature to reduce EMI from the output edge rate, and of course disable said feature if necessary.

[jwet]

Don't know what level of precision is required and this is coming from another direction, but you might consider a multi-tap silicon delay line or related.  Maxim and LTC, now ADI, still makes a few that have 5 taps with fixed "semi precise" delays between outputs.   They were once popular in DRAM circuits and ATE equipment, etc.  Accuracy is a few percent, operation is dead simple.  Look at Max1100 or search DK for delay circuits. Digikey still sells some and they're popular surplus parts.

At your speeds, you might even be able to get away with just old 74C cmos jelly beans, they have prop delays on the order of your delays.

Good Luck.

[marcov]

I'm a bit unsure about the 50ns, but you *should* be able to do it with a dsPIC33CK high speed PWM. You also have a retriggerable mode with a retriggerable counter, so you can generate up to 7 pulses after a trigger

Another solution for the dspic33 range:  Output Compare in dual compare can be trigger from an INT .   If you can get a no code solution to rearm the OC after one cyclus, it could be quite fast.   You could use the OC interrupt to retrigger the OC, which would still be only in the 1-2us magnitude.

[NorthGuy]

Or use PIC16F13xxx. They have a tiny FPGA inside with around 30 LUTs, programmable in Verilog, which you can interconnect with timers and other periphery.

[fracton]

Thanks a lot! That was really helpful. I was wondering if I could trigger pulses C and D at the falling edge of my input pulse. In that case the pulse width of my input pulse would determine the delay between A_B and C_D.

[mino-fm]

If you like to use my RP2040 program, you can add PIO-code:

// delay
  *prg++ = 0xa046;                              // mov y, isr
  adr++;
  *prg++ = 0x0080+adr;                      // while(y--); jmp y--
  adr++;

// additional wait until TRIGGER_PIN goes low
  *prg++ = 0x00c0 + adr + 2;              // if(!TRIGGER_PIN) skip loop
  adr++;
  *prg++ = 0x0000 + adr - 1;              // loop
  adr++;

// 2. pattern

It isn't tested but should work this way. Please notice: TRIGGER_PIN ist inverted by GPIO4_CTRL.