Zynq FPGA application with ADC proposed structure - please critique

[daqq]

Hi guys,

For a project I will be using a Zynq 7010 device, I would like to ask whether you'd choose this structure:

There will be two clock domains - one from the processing system (miscellany board control, a little processing), the other one will be clocked with a high speed ADC clock and will do some fast calculations and acquisitions. In general terms it should work like the simplest triggered scope - when armed and triggered (external logic, internal logic or ADC threshold value), the ADC samples N (~32k) samples into a fast memory, sets a flag somewhere, the processor reads the flag, reads the samples out and does its magic with them.

All of the functions should be memory mapped, via the AXI-Lite interface. My proposed base structure ( made out of existing IP) should be:

ZYNQ PROCESSING SYSTEM -> AXI to AXI Lite conversion (AXI Protocol converter) -> AXI Crossbar splitter into 2 AXILite busses

Bus 1 goes into the miscellany processing
Bus 2 goes through an AXI Clock converter into the other domain



The transfer of data between the ADC area and the processor itself does not need to be particularly fast, but I want it memory mapped - really awesome feature.

What do you think of the proposed base structure? Any refinements?

Thank you,

David