PCB layout for DC to DC converters to avoid ground bounce, EMI and other issues

[DaveCMechEng]

Hi Dave,

I designed my first PCB for a DC-DC boost converter only to find that it produced very noisy output. The design is based around the MIC2253 (http://www.micrel.com/_PDF/mic2253.pdf).  The design appears to give the correct RMS step up voltage on the output, but, after viewing the signal through an oscilloscope I see damped sinusoidal voltage oscillations appearing periodically which seem to be initiated by the switching of the inductor. The oscillations are large, that is 3 V peak to peak.  After doing a bit of research it seems that my problems are not particular to my choice of converter, but, to problems with my PCB layout (see links below). I don't understand how to fix my layout to ensure better results. This might be a good blog post to address best practices for DC-DC converter layout since they are often used in electronic design.

http://www.physics.ox.ac.uk/lcfi/Electronics/EDN_Ground_bounce.pdf
http://www.analog.com/library/analogDialogue/cd/vol41n2.pdf
http://www.enpirion.com/Collateral/Documents/English-US/High-frequency-implications-for-switch-mode-DC-R_0.pdf
http://www.maxim-ic.com/app-notes/index.mvp/id/3645
http://www.maxim-ic.com/app-notes/index.mvp/id/735


Thanks Dave,
Love the Blog.

[mobbarley]

Can you post some cad pictures of your PCB layout around the switcher?

[DaveCMechEng]

Sure thing...

I've attached three images. "original pcb.png" contains an image of the board I am having issues with. It is a 2 layer board. Red is the top copper. Blue is bottom copper.




"current loops.jpg" shows the prototype board with orange and yellow overlays of the two different current paths used to charge (orange) and discharge (yellow) the inductor. One of the articles, whose link I posted above, suggested that the two current loops should not change in area, thus, I tried to minimize their the change in area in a new layout I started in "pcb_fix.png". I hacked the original PCB so that it was closer to this new layout, but, the performance of the board didn't change. It is still noisy! The quality of the hack isn't as good as shown in "pcb_fix.png", however, it is a fair approximation. I would have expected somewhat of an improvement, but, I didn't see any.

I'm still not sure how to fix this. Maybe the ground pour is causing too much parasitic capacitance? Perhaps the caps have too much impedance (ESR)? I don't think so, because they are all ceramic multilayer and have the values and dielectric material requested by the datasheet, i.e. X5R.

Any help would be very appreciated.

Thanks,
Dave
 

[DaveCMechEng]

Not to take away anything from the eevblog, which I love and watch religiously, but, I also asked this question on the stack exchange:

http://electronics.stackexchange.com/q/22898/1900

I've posted the link here since I have got many responses and it doesn't make sense from a practical point of view to carry the conversation in two different places. I hope Dave will forgive me for redirecting a minuscule amount of traffic away from his site. Anyway, my initial point of posting here was to communicate with Dave L. Jones about a possible blog topic and I've succeeded in doing this.

[mobbarley]

I put some thoughts there to your question - stack exchange is great but it can be hard to get the right attention.

[Short Circuit]

Bottom trace and vias in the groundpath between C5 and the switcher are the problem.
Very high dI/dt there, so the slightest bit of inductance in the loop will cause ringing.
If you take a look at the sample layout in the datasheet, you'll notice that C5, D1 and U1 form a very close loop with short copper on top layer only.
Not uncommon with this kind of mistake to kill the regulator because of the resulting overvoltage, been there done that.

[DaveCMechEng]

Thanks Short Circuit,
Your explanation makes sense! Then, I was working somewhat in the right direction when I laid out the board again (pcb_fix.png) with C5 closer to U1 and D1 flipped around to reduce the loop size and thus its inductance. Although, the new loop is now on the top copper, there are some obstructions in the loop, i.e. vias. Will the vias in my new layout still add to the inductance of that loop even though they are not intended to be part of the loop? One of the vias, i.e. the one just below U1, is to connect the top and bottom layer ground and for thermal dissipation. The other via is between the inductor and the D1 and goes to the switching pin on U1. I.e. this point oscillates between being grounded and floating by the transistor on U1. They I may have to layout the whole board again following more closely the sample layout just to be safe and avoid these vias, but, I'd like to understand not only what to do but why I am doing it.

Thanks!

[Short Circuit]

Sorry, but that (pcb_fix) is not going to work any better. The GND part is fine now, but you created a new problematic connection between D1 and U1.

An easy fix is to take a bigger capacitor, like 1206 package, and route underneat to the inductor pad.

Or you could reverse the diode (cath down), rotate the output cap so its in the same position as the input cap, and move the indictor all the way to the right. Then you can realize the 'triange' layout between U1 D1 and Cout very easily. The feed from Vin to the inductor can go on the bottom with vias. No problem here because all these do is add some more inductance to L1.

The via between the capacitor and U1 is not a problem. Actually, I believe its pretty much the best location to 'inject' the ground.
Good luck