Electronics > Open Source Hardware

LCR/ESR Impedance Meter UA320

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unitedatoms:
Jan 2 2020: 5 years later. Starting new LCR meter project from scratch. UA320 (meaning 3 digit accurate, year suffux 20).
I will keep this same post for reporting on progress.

General idea: The 10MHz is more interesting challenge than original 100-200KHz meter. There is no much need in new low frequency designs because there is a lot of old designs. I hope that this challenge (to reach 10MHz) will keep me interested. Part of the reason, why I did not finish first model is that there is too many existing designs equally interesting and also winning the cost game (cost game is not very interesting part for me).

Approach to costs: Be reasonable, but somewhat ignore most of the cost related considerations at the phase of proving the concept. Lets define proof to be an accuracy in numbers alone (not in combination with cost).

Design choices: So far the 10MHz range dictates the use of RF method, (so named ?) balanced bridge with null detector.

What killed first project? Lack of knowledge, experience and attention to power supplies. Unnecessary feature to have a standalone display and enclosure before the analog modules were complete. Dead end with use of supercapacitors. It looks that supercapacitors have limited life span in terms of amount of charge / discharge cycles. Dealing with supercaps sucked most of available time for builds. Lack of experience with firmwares in general. Use of Arduino.

What should not be in new design: Skip Arduino story completely, do bare metal firmware with perhaps PSoC5 or similar. Skip display so far. Use either USB/Serial or Ethernet with high level software on Windows PC for concept proving. May be eventually add more of screen and knobs to make instrument a standalone.

What to focus on: High resolution of phase detection. Perhaps 20-22 effective bits at 10 MHz.

What is done so far: The phase detector works on paper (LTSpice) with accuracy of 0.007 degrees. And 0.000 degrees repeatability (because it is LTSpice).

What is next step: Review the phase detector alone. Build it and see how well it runs physically.

Description of project: The voltage signal is pure sinewave applied to HI of component under test. Another current controlled sinewave is applied LO of component to maintain zero. Three resulting quantities (voltage, current and residual zero) are detected by phase detector to determine I and Q quantities. The expected null residual value used to compute new applied values. The corrected new applied values appear at component. Cycle repeats. Some arithmetical aggregation, either sliding average or sliding median is used to recompute impedance quantities.

Measurement cycle: The duration of measurement cycle is defined by dual slope ADC (for example MAX132) to suppress mains AC interference at 60Hz. Expected rate of acquisition is 16 cycles per second. At start of each cycle, the V and I source signals are set to known relative phases and magnitudes. During cycle the V source and V2[Quadrature] source is fed to phase detector. There can be 1 or 2 phase detectors (to speed up measurements, the null detector is just another phase detector with less strict accuracy).

How many sources: So far it looks that 4 identical DDS will do. 1 for V signal. 2 for V2[Q] signal. 3 for I signal. 4 is reference DDS for transfer of high res phase/magnitude value from reference to 3 measured signals at the uncalibrated plane (input of phase detector(s)). Why transfer reference DDS is needed ? It will allow to never need a characterization/calibration of phase detector. Detector has limit of accuracy worse than desired resolution/accuracy, however has high repeatability, it is precise. To rely on good precision and bad accuracy, the arbitrary reference is needed. So instead of traditional complicated analog self tunable loops, which keep null detector at null, the loop is just a software routine based on matching reference to any of the signals.

How high the phase resolution is available: It can be up to resolution of DDS phase accumulator even if direct control of phase in DDS is coarse (16 bit), the 32 bit is achievable through so named sweep capability of some of DDS. The DDS is set instead of single tone to specific frequency plan with exact amount of clocks per step, delta frequency per step, amount of steps etc. to ramp through the plan after triggering and dwell at end frequency as normal single tone with phase continuity maintained. The frequencies in ramp plan can be set with very high resolution. So it gives full digital resolution of phase. The magnitude can also be resolved precisely using DDS analog pinout for current setting with external DC DAC.

===============text above is recenttext below is historical================
Nov 18 2018: old 2015 schematics and code attached for history.

I am excited to share with All my Impedance Meter project.
It is named UA315 Open Source Hardware LCR/ESR Impedance Meter. It can be either DIY benchtop kit or completely built.

The thread is being updated in real time as the project progresses

Blog posts, design articles, detailed info, (WARNING: picture of cute dog :))

Voting thread
Please add your vote to help me to understand what pricing can be!

Device description
It measures Immitance parameters: Impedance ( Resistance and Reactance ), Admittance (Conductance and Susceptance ). Capacitance, Inductance, Equivalent Series Resistance (ESR), Q value, D factor, Phase angle / Loss angle and Loss Angle Tangent in range of frequencies 10Hz to 100KHz (with possibility to reach 200KHz, but it is yet to be seen).



The project is about 50% done and I will keep posting schematics and code as I go.
The digital board is Arduino(TM) alike:

The analog-to-digital board is in progress. Waiting for first 5 analog-to-digital board prototypes to arrive so I could tune the custom made transformer details.

The Analog to digital board schematics:


There are 2 boards.
Digital board is 75+ parts.
Analog board is ~220 parts.
Also included parts:
- probe
- internal flat cable 34pin
- power connector
- enclosure with fasteners


The brief description of how analog-to-digital board works:
- The AD5933 is single bin Fast Fourier Transformer with Direct Digital Synthesizer used as magnitude and phase sensor.
- The excitation signal is buffered with op amp wired as phase-error reduction amplifier (p.314 of Art of Electronics 3rd ed.) also summing DC offset to provide DC bias to device under test
- Kelvin probe and device under test have current limited by output impedance of a buffer.
- The sense V of D.U.T. and reference resistor is scaled by instrumentation amplifiers
- V and I signals from instrumentation amplifiers are multiplexed and brought to AD5933 input through V-to-I resistor, since AD5933 accepts only current input.
- The data about amplitude and phase both for V and I is processed by Arduino-alike board and displayed to user.

Brief extra details, why the parts count is high:
- Major effort is done to reduce the noise of power supply
- All clocking of every chip is fed from single master clock generator with muxed dividers
- The power supply is supercapacitors banks (graphene based!) which supply power during controlled shutting off of the step-up DC-DC converter
- The power during measurement phase (from few milliseconds up to 1 sec at 10Hz range) is regulated with linear regulators, there is no switching, transitions or power source disturbing software activity is happening during measurement phase
- The external power is isolated to >100-120 Db during measurement phase
- The relays are latchable and are not powered during measurement, so the contacts resistance is not modulated by coil current fluctuations
- The method, algorithm and implementation is done with care to avoid reliance on absolute voltage
values. The design is completely ratiometric, so the major contribution to accuracy is values of reference resistors.
- The DC errors like offsets instabilities, thermals are not affecting the AD5933 converter since it has narrow-band sensitive to only single frequency bin
- Having no need to avoid DC errors, the signal path has no DC blocking capacitors, it adds stability to output buffer and reduces risk of parasitic feedbacks
- Having separate I and V channels, which are measured at separate time, the geometric calculations made possible to move from analog-to-digital part and perform in software, instead of AD5933 original designs, where  measurement relies on assumption that output signal has certain phase.
- Having 2 pairs (I and V) of phase/amplitude data instead of 1 assumed pair and 1 measured, the phase accuracy measurement may exceed the one claimed in AD5933 datasheet
- Having this 2 pairs of data, the design is immune to accuracy of output buffer and does not require the buffer to become a critical part of signal path, like Howland current source, transformers, calibration or highly precise parts etc.
- Replacing I-to-V amplifier with virtual ground with simple reference resistor helps to avoid reliance on phase accuracy of I-to-V converter. Resistor is assumed to have no phase dependency of I-to-V conversion (at least in range of frequencies of interest)
- In low and middle ranges of D.U.T. impedances the probe capacitance is factored in calculations and shows the predicted behaviour.
- For high impedance and low and midrange frequencies the probe capacitance factor is also trivial.
- The only difficult range is high impedances at high frequencies. To resolve this difficulty the prototype #4 (this is 4th iteration since April 2015) has instrumentation amplifiers added. It were simple CMOS followers in prototype #3.

The code is about 25-30% ready:
It is about few hundred lines of Arduino Sketch language. It uses UTFT library. The algorithm is infinite loop repeating the measurement and display. The calculations are all straightforward without magical constants or reference values without physical unit. It is as deterministic as possible, the factored values for parasitics like probe capacitance are explicit and are introduced in understandable, easy to maintain manner.

I will publish my very raw code as soon as will complete the analog board ordered from SeeedStudio and complete the transformer design.

Update Sep 24 2015:

The digital subassemblies progress: 34 out of 50 subassemblies for 50 kits are done
The analog boards are on the way from Elecrow.

DmitryL:
Hmm... woud you share the device specs first ?
You know, these boring numbers, like: "xxx mOhm- yyy Mohm, zzz pF- www mF, qqq nH- ppp H... with ABC% tolerancy..., test frequencies:bla-blah..."

unitedatoms:
Yes, absolutely. The specs are preliminary, some are underspecced, some other are too ambitious. I posted it in Crowdfunding section of the forum to get the price poll. Depending on what people think about costs, I will choose most appropriate final specs. For example 0.1% 5ppm resistor is one cost, but 0.01% 2ppm is completely different price range, and so on from component to component.

Release Date:
October 2015
 
Brief Product Description:
UA315 is a reprogrammable benchtop impedance meter for frequencies up to 100KHz. It is Open Hardware and Open Source device designed for electronics enthusiasts, who make their own electronic lab devices.
 
Technical Specs (preliminary design targets):
Model Name: UA315 (revision Beta Aug 2015)
Accuracy: 0.5% or better
Resolution: 3 or more digits
Impedance range: 0.001 ohm .. 1000 MOhm
Frequency range: 10Hz .. 200KHz
Excitation AC voltage: 1V or less
Excitation DC voltage: 2.5V
Protection from input voltage: Up to 500V
Power supply port: 5V / 1A round 5.1mm DC connector with cable for USB style power supplies or any other DC power supply. (Power supply is not included with device, when sold as assembled product or kit)
Dimensions: Approx 4" x 13" x 2"

The L and C specs are yet to be decided: But very preliminary it should be.

0.1pF .. 0.1F
10nH .. 1000H

The lowest values are most difficult.

DmitryL:
Looks nice.... tough dubious..a bit. :-/
Have you tried to apply to Agilent/whatever as a chief technical architect, just in case ?

unitedatoms:

--- Quote from: DmitryL on August 06, 2015, 09:20:53 pm ---Looks nice.... tough dubious..a bit. :-/
Have you tried to apply to Agilent/whatever as a chief technical architect, just in case ?

--- End quote ---

Ha ha. No. This project is much smaller caliber. May be at the level of "Jr. Design Engineer". If it was the Chief Architect level, I'd use custom hybrid chips and gold plated parts on sapphire ceramic substrate.

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