I'm not sure why the ST app note has such poor waveform quality, it looks like breadboard quality in some scope traces

2.2.3 "In this case hysteresis (implemented, for example, by a positive feedback loop) is not recommended as it could influence the distance between the signal edges."
But you have it in your design. I would not bother with the comparators as the signal is strong at 0.2-0.6Vpp and I'm not sure if fidelity gets affected. It seems jitter issues fall into audiophoolery, cable voodoo and long winded arguments. Most SPDIF designs are using 'HC04 gates as the receivers.
For 192kHz (12.28MHz) I would be adding resistors at the IC outputs to lessen transmission line effects with your PCB layout. I start with 33R, you can put in 0R if you want but I leave a provision for termination resistors, usually they are needed to stop ringing and overshoot from being a problem.
Other people here know more and probably suggest how to keep the waveforms crisp.