For the video you linked at about the time you mentioned, the current passed into the first core,
and between the first and second core, are only pulses. Not continuous current.
You can think of the first core setting the second core as a single action that happens once, and very quickly.
The winding around the first and second cores is a secondary on the left coil, and a primary for the second core in the right coil.
Thanks again!
That makes sense.
Also, in the meantime I've also rewatched that video
I'm convinced that (if I wanted to, or need to in the future), I
CAN fully understand those videos, and core memory/logic concepts/techniques, as and if necessary.
I was being thrown (into NOT understanding it) because I was expecting it to be like "Normal" TTL logic like concepts.
But in reality (as you have just kindly explained above), it is NOT stationary logic 0 and logic 1 levels. As you would have in a TTL (and similar) logic device/circuit. Which are (typically) waiting for the next clock transition. Then the logic states will rapidly change again.
But a flow of what are essentially pulses.
Hence that is why I was having difficulty understanding it (the logic side of the core memory used as logic circuits).
Where I am a bit disappointed in that video I LINKED TO is that he suddenly introduces the concept of multiple cores (coils), connected together. WITHOUT (apparently) explaining why there are multiple cores and what the multiple cores are going to be used for.
I did not realize that understanding how core memory logic circuits work (especially as regards multiply connected core memory elements, to perform computing logic functions), would be so difficult to understand. When one is use to the "static" TTL logic way of doing things.
I guess most logic things these days are clocked (synchronous). Which although core memory/logic are also potentially clocked/synchronous as well. They are potentially relying on various pulses, flying through the system. In order to make shift registers, and other computer logic functions.
Or to put it into different words. What I mean is that if a modern day TTL/FPGA system, was to greatly slow down or even stop its clocks. There would be greatly slowed down (or even frozen) logic levels to observe. Potentially making it easier to understand and experiment with.
Whereas these core memory/logic systems, appear to always need these relatively high speed/fast (to us humans), pulse transitions. In order to function.
It is a bit like some very, very old logic (discrete germanium transistor), which had speed up capacitors, across various resistors (a sort of RTL logic, Resistor Transistor Logic). So that there was a sort of high speed part to the signals. Even if it is clocked at very low speed.
tl;dr
I reasonably fully understand how basic core memory works, as regards simple read/write operations. Thanks!
I somewhat/partially now understand how core memory/
Logic. Such as (transfer) shift registers work as well.
If I ever end up making stuff like that and/or repairing stuff like that. I will then spend the time to much more fully understand the intricacies of how it is done. But I have enough of a grasp now, to have a partial understanding of how the more complicated aspects of core memory/
Logic is doing its stuff.
Anyway thanks again for all the explanations!
As time goes on (after your explanations and rewatching the video). My understanding is getting, better and better. I bet that if I was to actually try and make some core memory and/or core logic types of devices. I would have many more technical issues/problems. Which I just don't realize about at the moment.
Finally, thanks for explaining where you got the ferrite cores from. It is amazing the stuff you can get on ebay.