Computing > Programming

Can I increment an integer faster if 'step' is a power of 2?

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--- Quote from: rstofer on July 12, 2021, 09:57:44 pm ---
--- Quote from: SiliconWizard on July 12, 2021, 05:22:22 pm ---
Of course. One obvious point here - the OP's question sort of assumes that regular integer addition could be more expensive than some other instruction on a given target. This is very uncommon. I don't think I have ever seen such a target myself, or it's so old that I don't remember.

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Some designs (like ARM) have an 'add immediate' instruction where the increment is encoded with the instruction for small values on increment (0..4095).  Otherwise, the operand is required to be in a register and this may require an indexed fetch from a pool area of constants.  The value 'may' be in a register but I don't think you can assume it is unless you play with assembly coding

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Many ISAs have "add immediate" instructions. Obviously if the increment can't fit an immediate, you need to load it first in a register. Depending on surrounding code, this register will hold this constant every time the increment is done (in a loop), or it may have to reload it every time (could be also done 'indirectly' by register save and load if you are calling functions in between, or all registers are used up, or interrupts kick in.) Note that in cases it has to load a register every time with the constant, that usually means a significant number of instructions have been executed in between, and then one instruction more or less won't make a fricking difference. That's not even micro-optimizing, at this level. It's nano-optimizing? ;) Just a thought.

Of course for "add immediate" instructions to be used, the increment must be known at compile-time.


--- Quote from: 741 on July 12, 2021, 01:23:17 pm ---
--- Quote from: gbaddeley on July 12, 2021, 12:34:16 pm ---Integer Increment is basically the same low level logic complexity as add

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Thanks, that is what I suspected. This is on a PIC, and it is ages since I used assembly. The loop speed matters, since I want low overhead to be sure that N fixed delays add up to what I intended  (N * fixed delay). I have to take the ADC sample at the correct time relative to initiating the readings.

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On the lower end PICs at least, decrementing the loop counter can shave a few cycles because the decfsz instruction is pretty much all you need.


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