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Algorithms and Patterns for implementing an ICE Processor Emulator
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Topic: Algorithms and Patterns for implementing an ICE Processor Emulator (Read 3449 times)
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obiwanjacobi
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Algorithms and Patterns for implementing an ICE Processor Emulator
«
on:
August 26, 2019, 05:22:39 am »
I am trying to implement a Z80 ICE emulator to run in a PSoC5 and have the beginnings of the code working.
However I have some questions about the correctness of my approach and created a StackOverflow post for it.
https://stackoverflow.com/questions/57643974/what-algorithms-and-or-patterns-to-use-for-an-in-circuit-processor-emulator-z80
To be clear: this is software that exactly tries to behave like a real Z80. It changes state on every (half) clock-cycle. It activates signals (RD/WR/MEMREQ etc) at the correct places in time etc.
Please chime in if you have any experience writing this kind of software or know any theory.
[project]
https://github.com/obiwanjacobi/Zingularity/tree/master/Source/Jacobi.CpuZ80
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Wrong code should not compile!
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