FPGAs
FPGAs don't need anything else, just VHDL and Verilog (perhaps also SCALA, which outputs VHDL and Verilog)
They don't, but that doesn't stop people from trying to come up with something "better."
While I myself said that I wouldn't use one of those "higher-level" HDLs and would stick to the standard ones for a number of reasons, I'll still honestly admit that it has proven to work in some cases. SiFive has been successful using Chisel and I don't think they have a plan to switch back to Verilog or VHDL any time soon. (Now if Intel does acquire SiFive as was being discussed, things may change, but also as we discussed, Intel's main reason for buying SiFive if they ever do may not be directly reusing their cores anyway...)
I started
here. I found and spent some time reading through
The Chisel Book and ... I don't see where Chisel is better than VHDL or SystemVerilog. Honestly. The syntax is different. The book also has an odd statement:
10 Hardware Generators
The strength of Chisel is that it allows us to write so-called hardware generators. With older hardware description languages, such as VHDL and Verilog, we usually use another language, e.g., Java or Python, to generate hardware. The author has often written small Java programs to generate VHDL tables.
"Generate hardware" must mean "generate a table that gets synthesized into a ROM." Because other than that, I've never written a Python script to generate hardware! I honestly don't know what is meant by that statement.
The main Chisel page has a link to a Stack Exchange
article full of sound and fury, but signifying nothing, as it doesn't actually answer the question posed.
One of the things that seems weird to me is that it has a notion of an implicit clock for registers. Many FPGA designs have multiple clocks, and it is really handy to know which clock is driving which elements! And it would be interesting to see an example of how to manage clock-domain crossings in Chisel.
I don't see how Chisel allows for instantiation of black boxes for FPGA features like deserializers and other I/O things, clock management blocks and the like. Perhaps someone has written libraries which present those features as modules you instantiate, and there's some magic under the hood that manages this?
Does Chisel support parametrized design and generics and the like? Can I instantiate multiple copies of a lower-level entity like I can in VHDL with a generate loop? I have some designs here which has a "channel" entity which can be replicated simply with such a loop.
I'd like to see an example of a small but complete hierarchical FPGA design written in Chisel. The design should include lower-level entities/modules/whatever as instantiated in the top level. Some of those lower-level things should themselves instantiate even lower level things.
Anyway. I'm honestly open to learning about why Chisel/Scala could be better. But for my designs, which tend to be kitchen-sink collections of stuff with a bunch of external peripherals which need servicing, I don't see the advantages.