Writing a compiler backend

[coppice]

Up to GCC 3.x it was a great platform for the MSP430 and AVR backends. After that it all went pear shaped. We could never get as tight code for either of those architectures from GCC 4.x, no matter how much massaging we did. The stuff they put in to improve scheduling in complex cores just degraded what it could achieve for simple cores. I think they just didn't care

Who is "they"?  GCC is open source. The people who maintain and improve performance or code size or whatever on any particular ISA are the people who care about that ISA -- the users of it. If no one cares about an ISA enough to maintain the back end for it (past minimally working) as the rest of the compiler changes and improves, then the only people to blame for that are the users of that ISA. Or the lack of users.

What on Earth are you bladdering on about? They is obviously the developers of the main line GCC code. We, as developers of ISA back ends trying to eventually get them into the main line were playing constant catch up, and had no say. Conceptually the core of GCC is supposed to be ISA neutral, but of course most of the development of the core is driven by people who have specific ISAs they are trying to optimise for.

You do know that GCC 4 is twenty years old? There have been a LOT of versions since then.

GCC 5.1 is less than 9 years old (22nd April 2015, I just looked it up). I think they skipped 5.0. So, the GCC 4 series was very long lived. After that they suddenly started jumping the version numbers rather quickly.

The main ISAs that I use (arm64 and riscv) didn't even exist -- hadn't even been contemplated -- when GCC 4 came out. RISC-V RV32I and RV64I exist in very simple cores (as well as more complex ones) and modern GCC handles them well.

ARM64 was in the later revisions of GCC 4. I think RISC-V must have been too.