EEVblog Electronics Community Forum
Electronics => Projects, Designs, and Technical Stuff => Topic started by: opa627bm on September 02, 2022, 05:16:21 am
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Hi all,
I am trying to make a small dual slope ADC for 0 - 24V in only and I was happen to find a Data Precision 3500 that have decent range and not everything is integrated.
After reading the service manual.
http://w.ko4bb.com/getsimple/index.php?id=download&file=06_Misc_Test_Equipment/Data_Precision/Data_Precision_3600_5_12_Digit_DMM_Service_Manual.zip (http://w.ko4bb.com/getsimple/index.php?id=download&file=06_Misc_Test_Equipment/Data_Precision/Data_Precision_3600_5_12_Digit_DMM_Service_Manual.zip)
I have few questions for the analog front end section (page 21)
1. why the differential amplifier Q6 - side is going in to positive side of the OPAMP Z1 and + side is going to negative side of OPAMP Z1?
2. Can this Q6 Z1 combo be replaced with a DIFET OPAMP (like OPA627?)
3. The gain section (described in page 20) , stating that when Q9 is on the Gain is 5 ( I can verify that with actual value), but when Q9 is off and Q8 on, the Gain is 50, however, it is AC coupled in to the negative terminal of the compound opamp, is that means the DC gain is going to inf ? how this thing will work? I noticed there is a per charge cycle for the cap C6 but not sure how it works in DC condition.
Thanks for the reading !
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The Q6 part is inverting (the labeling in the detailed schematics is misleadin with D and S swaped , which does not make much difference for symmetric JFETs).
The Q6 + Z1 comibation could be replaced with a moder FET based OP-amp. I would prefer an OPA140 over the OPA627.
The capacitance in series to Q8 is indeed a bit strange. I would guess this is part of some auto zero function. So there may be times with Q8 and Q9 enabled.
From the description it looks like the actual ADC is made for something like a 2 V input range. The 20 V part is with an extra buffer and divider.
The circuit is quite old, using mainly JFET switching. Today CMOS switches are available that can simplify things a bit. For a 24 V input the dual slope ADC type may not be the best choice.
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1. Q6a and Q6b invert the signal between base or gate, input, and collector or drain, output. That is why +ve Q6a goes into -ve Z1.
2. Are Q6a and Q6b JFETs? BJT transistors have generally, lower noise and higher gain than alternatives, JFETs higher impedance and lower bias currents. But modern opamps have vastly improved over previous years so a suitable replacement could be possible without the need for the matched pair Q6a, Q6b.
3. Not sure, will look into it further, perhaps others will know.
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The Q6 part is inverting (the labeling in the detailed schematics is misleadin with D and S swaped , which does not make much difference for symmetric JFETs).
The Q6 + Z1 comibation could be replaced with a moder FET based OP-amp. I would prefer an OPA140 over the OPA627.
The capacitance in series to Q8 is indeed a bit strange. I would guess this is part of some auto zero function. So there may be times with Q8 and Q9 enabled.
From the description it looks like the actual ADC is made for something like a 2 V input range. The 20 V part is with an extra buffer and divider.
The circuit is quite old, using mainly JFET switching. Today CMOS switches are available that can simplify things a bit. For a 24 V input the dual slope ADC type may not be the best choice.
Sir,
thank you very much for the response.
Do you know what to look for when finding a replacement OPAMP in this case ? (Opa140 vs opa627)
My plan is to have a high percision 10:1 divider so 24V in - > 2.4V max.
Of course, another easy way for this design is to slap a 32bit ADC with LM399 with a 10:1 divider...
Regards,
Li
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With a divider in front and than some 2.5 V voltage range a dual slope ADC is practical, though still a bit outdated. No need to go high end to compete - a dual slope has a hard time to compete with something like a simple MCP3421 chip ( 18 bit SD ADC with reference in SOT23-6 case).
For most cases the dual slope ADC is more like a thing for educational purpose, not really competative anymore. About the only good point is the good gain stability.
For the amplifier (often buffer) at the ADC input the point to look for are low frequency noise (e.g. the 0.1-10 Hz noise), maybe the DC drift and depending on the input circuit also the input bias.
With the limited performance of a dual slope ADC one may not even need absolute highest performance and a cheaper part like TL072 may be good enough.
Anyway the choice of amplifier chips is more like one of the last steps, only after the overall circuit or at least the block diagram is ready. Up to that point the choice of amplifiers is more like one of the amplifier classes (e.g. precision, high speed, low bias, zero drift, low cost) that may be represented by typical ones (e.g. OP07, LM318, LF351, ICL7650, µA741) , but open to later change and use modern types.
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With a divider in front and than some 2.5 V voltage range a dual slope ADC is practical, though still a bit outdated. No need to go high end to compete - a dual slope has a hard time to compete with something like a simple MCP3421 chip ( 18 bit SD ADC with reference in SOT23-6 case).
For most cases the dual slope ADC is more like a thing for educational purpose, not really competative anymore. About the only good point is the good gain stability.
For the amplifier (often buffer) at the ADC input the point to look for are low frequency noise (e.g. the 0.1-10 Hz noise), maybe the DC drift and depending on the input circuit also the input bias.
With the limited performance of a dual slope ADC one may not even need absolute highest performance and a cheaper part like TL072 may be good enough.
Anyway the choice of amplifier chips is more like one of the last steps, only after the overall circuit or at least the block diagram is ready. Up to that point the choice of amplifiers is more like one of the amplifier classes (e.g. precision, high speed, low bias, zero drift, low cost) that may be represented by typical ones (e.g. OP07, LM318, LF351, ICL7650, µA741) , but open to later change and use modern types.
Thank you for the response!
I have talked to my Dad during the weekend and I started to make some sense of the circuit.
1. During the pre charge state (both switches turned on ) , both feedback arm turned on, so assume compound opamp is in stable stage. then the voltage between the cap C6 is 1/50 * Vin and Vin. When switched to 50 Gain stage, it will be stable for a while untill it start to discharge.
2. If Dual slope is not really that competitive anymore, why most of the bench DMM still using this technique ? The reason I choose it is because i though there are some key advantage to it, otherwise I will just slap a >=24bit ADC and call it a day lol.