[Poll] FPGA board form factor

[blueskull]

I'm working on a Gowin Arora GW2A-18 FPGA module for integration and prototyping.

Which form factor do you think it's the best if you are looking for an FPGA module?

I'm aiming at development prototyping and very low volume prototype production runs.

FYI, the design features are as follow:

1. 21k 4-LUTs+16k FFs
2. 42Kb distributed SRAM+828Kb block SRAM+64Mb SDRAM
3. 48 M18 DSPs (24 DSP slices, each can be configured as dual M18 or single M36, both come with MAC/ALU options)
4. 2 PLLs+4 DLLs with on board 12MHz clock
5. 34 IOs in 4 1.2V~3.3V banks+31 IOs in 3.3V banks, most IOs are true LVDS capable
6. On board SPI FLASH+FTDI downloader+FTDI UART
7. Supports Cortex M1 (from Gowin), RiscV (from Gowin) and ZPU (from me)
8. On board PMIC accepting single 3.5V~5.5V input with input voltage sensor
9. On chip USB HS PHY IP (under development, using DLL, PLL and IO gearbox), tentative
10. A few LEDs for heart beat and debugging, maybe one or two micro buttons

As for form factor, I intentionally left out castellated hole option as I simply don't like it. I also left out HumanData's PLCC form factor as it's just to expensive.

Target total BOM is <$15 at 100 pieces batch.

Poll locked. Final form factor: DIP gum stick with micro USB-B and FPC expansion connector.

[DaJMasta]

Are LGA modules that easy to assemble into a low volume product?  Castellations would be hand solderable and as a result don't require anything fancy (not that I'm saying you should use them), but would an LGA module need special oven profiles or handling to use properly?  Could limit viability in small production runs, even though the overall cost is probably the cheapest.

I'd think USB C would be most desirable to the hobbyist level user, but it probably counts for less in commercial or industrial development environments.  If the mezzanine connectors themselves aren't too expensive, I'd probably go that route and make a breakout/development board with the mating mezzanine connectors and the USB C.  That way you have an easy-to-integrate module with a lower base price and a carrier board for more convenient prototyping.

If you were thinking of aiming primarily at the hobby market, maybe the USB C alone would be preferable, since the combination of a module and a carrier board would likely be a fair bit more expensive.


LGA is probably the cheapest to use in production runs, but it would probably be a pain to develop on.  Maybe if you had an LGA module and a USB C carrier board you could develop on the carrier version and then integrate only the module into the product - maybe a good balance in usability and price, especially if the mezzanines are going to be expensive or really low profile is an advantage.

[james_s]

I like 0.1" pin headers for GPIO and some more specialized connectors for high speed stuff like LVDS. It really depends on what one wants to build though.

[Berni]

To be honest i don't really see the point in having a carrier board for such a FPGA chip.

From a quick look over the Gowin GW2A series its available in QFN and TQFP packages and if you want lots of pins also available in the nice big 1mm pitch BGAs that are reasonably easy to solder by hand. So if you are designing a board for this module to fit onto you might as well just solder the chip directly to it. The chips also look reasonable in terms of external support circuitry. Just needs 3.3V and 1.1Vcore and a SPI flash and on a small FPGA like this the Vcore could even be done with a simple LDO.

Yes 0.1in headers are the most friendly for prototyping but usually existing dev boards out there already offer plenty of those. What i have went to for my recent Lattice board is 0.5mm FPC connectors. This allows you to connect other boards to it via a flexible cables for convenience and a FPC connector is pretty easy to solder. These FPC cables can perform very well at high speeds if you put a ton of grounds on the pinout. No need to bother with fancy high speed cables, all you have to do is alternate signal and ground traces and this forms a nice transmission line, works well for LVDS too (In that case you go GND D+ D- GND D+ D- GND ...). Works with 1.27mm pitch ones too but not quite as well (I had 600Mbit MIPI running just fine over one of these tho).

[jhpadjustable]

There are FPC to DIP breakout boards all over Aliexpress. I'd imagine them suitable for extending I/O to the experimenter.

If you keep enough important signals at the edge and at roughly 1.27mm pitch, and place higher-density signals and returns near the center, a hobbyist could build a simple footprint with long-toed pads and nothing in the middle, then hand-solder the module to their board as if it were a large, wide-pitch QFN without wettable flanks.

[chickenHeadKnob]

I chose "gumstik" only because I assumed this means card edge fingers down one side, and then thought maybe you use this term differently. Mezzanine boards with different connectors are a non-starter. If more than one connector the mezzanine board should  only be one connector height/type, I suggest samtec.

I also agree with Berni, the low pincount devices are easy to solder and I would just include the footprint on my own PCB.

I haven't been following the GOWIN threads closely, how fast can the RISC-V core implementation be clocked?

[SiliconWizard]

I'd vote for castellations as well (but that can be a bit costly to manufacture), otherwise the LGA thing. The version with 2.54mm TH and an FPC connector is nice for simple prototyping stuff, not so much for integrating with another PCB frankly. And I'd like to see more IOs broken out as well.

Of course you could offer both versions, which would address two different sets of needs.

[Kilrah]

Keep the holes, AND add rows of castellations with more IO next to them. Those who want breadboard use the TH IO, those who want SMD use the castellated IOs, those who want loads of IOs find a way to use both that suits them.

[coromonadalix]

quote : Total board size is 18mm*36mm, and is wide DIP24 socket compatible.             Thats fine with me,  bread board compatible  etc ...   

We had to design a special board at my job  to replace a xilinx xc9572  with an atf1504,  the board has castellation, and i can tell you for us its a nightmare to solder, sometimes the pads bridge together, we had to use a finer solder paste ... the castellation is not perfect on the board edges, sometimes i have to use a filer to clean it a little, its depends where your boards are made and the quality they can do / provide you.

For me its a no no

[pigrew]

If there is a spare FPGA pin, it would be good to be able to disable the oscillator (controlled by the FPGA) for low-power modes.

Power supply is always a tricky thing. It'd be nice if one can power the board from either 3.3V or 5V. Does it work if I connect 3.3V to the VEXT pin, or do I need to connect it directly to the V3V3 pin?

I've started to really rather USB-C over micro-USB due to their robustness. USB-C is about 9x8mm, whereas microB is ~6x7. Could enough of the port be hanging off the edge of the PCB that they are about the same?

How do you plan to do the USB? Bit-banging? Or is there a PHY? Is the differential transceiver in the FPGA good enough to serve as a PHY? What about enable-disable of the USB pullup? Is it full speed or high speed? Would something like USB3322 fit? On the other hand, I have not had any use cases where I would need high-speed.

I don't have the datasheet open, but are there clock input pins that are broken out?

Since it's being through hole, are there any components on the bottom? Maybe add a footprint for SDRAM (or something else?) on the bottom that the user could add, which wouldn't be part of the standard build?

Is one able to both program the flash (for non-volatile usage) and the SRAM of the FPGA (for debugging)?

[ali_asadzadeh]

which PCB software are you using? I hope you use Altium!

[OwO]

Since this is very space constrained I think it's a good idea to not adhere to a fixed stackup. It is possible to have an effectively solid ground even if every ground plane looks cut into pieces if you have vias stitching them in in strategic places. I would highly recommend placing passives on the bottom side of the board because it would provide better decoupling as well. I would personally also put the spi flash right under the FPGA. At 18*36mm this doesn't look very difficult to route at all, so I can volunteer to do the PCB layout but I can't do altium (gEDA only).

[OwO]

When I design boards I never dedicate layers to roles; all layers are treated equally. Every layer starts off with a solid ground fill, and components are placed on either side in clusters to minimize distances. From then on routing is very ad-hoc but there are a few rules; high speed signals require a solid ground plane but only right under the signals. It doesn't matter if the ground is broken elsewhere so I route low speed signals on the ground plane at will provided it doesn't cross any high speed traces. There are also a few circumstances where you *can* run a trace under a component, for example if that component is a decoupling cap because its body is considered RF ground. Typically most passives on the bottom side are for decoupling so I generally prefer to route signals on in2. There is, of course, a ground fill on the bottom side but it need not be solid because all the "breaks" caused by decoupling caps are not considered breaks.

[OwO]

The BOM doesn't look very optimized, but these things stand out:

1. Really seriously consider alternatives to the FT2232. It's a big cost adder and even if you need true usb-fifo-gpio functionality a cheaper micro can usually do the job for under $1.
2. Please avoid SiTime MEMS oscillators. They cost more than surface mount TCXOs and the performance is way inferior to cheap smd powered crystal oscillators, which are easy to find on LCSC.
3. The choice of connectors seem on the expensive side; I would suggest starting your search on LCSC rather than digikey/mouser because you will often find low cost good quality connectors from Japanese or Taiwanese manufacturers that you won't find on digikey.

As it is the BOM cost is higher than the NanoVNA V2 

Also maybe add a pdf schematic because I can't open those files. Better idea, switch to kicad/geda or at least easyeda 

[OwO]

Just noticed the tantalum caps 
47uF isn't a very large capacitance for standard MLCC at 1.0V. That tantalum has an ESR of 300mOhm which is kind of shitty (a 22uF MLCC will have < 100mOhm). I would recommend 2 x 22uF 0603 MLCC caps instead; you probably don't want to use just a single cap for the entire 1.0V rail (I would go for 4 caps, one for each "side" of the FPGA, but 2 most likely will work).

[SiliconWizard]

1. FT2232H is a must. Gowin's official programmer software uses FT2232H's MPSSE mode to implement JTAG. I can dumb it down to FT232H, but for $0.8 saving, neutering a second channel which can be used for UART, is not the best option.

Yep. Funny how many people go bonkers as soon as they see the word "FTDI" somewhere. Yet FTDI parts are everywhere. And they just work.
And yes, for JTAG access, they are great. Many vendors' programmers use them, because their MPSSE engine works great for JTAG/SWD, and is trouble-free.

Just one suggestion. If it's "routable"... because your board's going to be pretty dense already.
It would be nice if you routed all required signals from the second channel of the FT2232H to access it as synchronous FIFO (I don't remember if you can use the second channel in synchronous mode, something to check). That's basically an 8-bit data bus, a clock out signal and a few control pins. The synchronous FIFO mode is the only one with which you can get the max data throughput (~30MBytes/s in practice).

Ignore that if 1/ channel two can't be used in this mode and 2/ you don't have enough room to route that, or enough spare IOs...
But just saying, I find it a shame that many dev boards using a FT2232H or FT232H don't allow you to use synchronous FIFO mode. UART only access gets you like 300KB/s max (for the highest baud rate of 3MB/s), asynchronous FIFO mode, only like 8MBytes/s max (which is already much better), but for only 1 additional pin (the clock), you can get the full throughput...

[SiliconWizard]

Ok nevermind... maybe you can think about that for a bigger dev board or something.

[OwO]

I think you are overestimating the tariffs. The cost difference between mouser/dk and shenzhen market more than makes up for the tariffs. I think a better option is to do everything from china and ship directly to end users while underdeclaring value. Most of the parts you are using don't really need to be imported.
 
I still think more effort needs to be put in BOM cost reduction because at $20 (and that doesn't include assembly) you will probably have to sell at $50 or so, which is a bit much for a module that people are going to incorporate into projects. de0-nano has existed for years at a lower price point so why wouldn't people just buy that?

If JTAG is for programming only, look into implementing the protocol on a micro and providing your own programming software. USB FS is fast enough to transfer the bitstream in 1-2 seconds.

$1.5 for a fpc connector is BS. I would move decoupling caps to the bottom of the board and use an ordinary FPC connector. Specialized parts should be avoided whenever possible.

With a bit of effort I think the BOM cost can be reduced to $10 or so, which means a sell price of $25 which is far more competitive.

[OwO]

A 1 minute search found this: https://item.szlcsc.com/305537.html which fits 30 pins into 17mm. Really look harder and look beyond the western brands next time not to mention Molex is known for subpar quality given the price.

[BravoV]

As enthusiast, just want to say I am grateful and conveying my appreciations reading the intense technical discussions of you two. 

Back into observing, learning and lurking mode.

[OwO]

1. ePacket is actually available to individuals; I ship like 5 packages a month and they still keep my account open. You have to first register on shipping.ems.com.cn (I just filled in "N/A" for 公司名称 and they didn't say anything about it), then contact EMS customer service to ask them to activate your account. (You need someone who can speak chinese for this part). The prices are posted here: http://shipping.ems.com.cn/product/findDetail?sid=400032

One thing to be careful about is China Post and EMS are separate divisions, and if you walk into a random China Post office they will know absolutely NOTHING about ePacket and quote you outrageous prices. You must go to a EMS logistics office which are more rare; one way to tell is that these look far more messy (big room, packages on the floor everywhere).

In shenzhen there are also proxy shipping services that will let you access far more shipping methods (e.g. postNL which is cheaper for EU destinations, and other methods that allow shipping lithium batteries). The prices are comparable to ePacket. You only need to take a short walk around HQB to find these. There are so many misconceptions about shipping from china on the internet that I don't know where to begin.

2. https://shop.trenz-electronic.de/en/TEI0003-02-CYC1000-with-Cyclone-10-FPGA-8-MByte-SDRAM?c=480
For a rough overview of market position:
$18 - Anlogic EG4, 20000 LE - https://www.seeedstudio.com/Sipeed-TANG-PriMER-FPGA-Development-Board-p-2881.html
$35 - Cyclone 10, 25000 LE, small form factor - CYC1000
$60 - Artix 7, 100k LE - "QMTECH core board"

3. OK that makes sense. In that case I would put the effort into looking for a clone or make a clone 

[ali_asadzadeh]

Please Stick to Alitum

[OwO]

Looks pretty good now 
Make sure to use pins from the same IO bank on the stm32 for JTAG interfacing; that way DMA can be used to transfer commands quickly.

[coromonadalix]

maybe add an daughter board / breakout board project for your fpc 30 pins connector

[OwO]

A suggestion, you might not want to expose your real name and details like that; I think it's a good idea to always operate under fictitious names and identities and never link them; see here: https://www.eevblog.com/forum/chat/richard-stallman-(gnu-dude)-resigned/