Buck converter PCB design - what I did wrong? (noob questions)

[Komajster]

Hello!
I designed my own DC/DC Buck converter, based on the LTC7803 (https://www.analog.com/media/en/technical-documentation/data-sheets/ltc7803.pdf).
I really wanted to use an IC with external power mosfet's, just because I think it is cool and because I needed a relatively high current output (up to 10A @ 5V).
I made the first revision of the PCB look like this:


And this actually works, but the switching waveform looks... bad



Also it produces a lot of audible noise while operating.
It already failed once (I don't know if it did so by itself or I did accidentally short the output and then it happened, but then the IC should protect itself I think). The high FET was shorted, after swapping it the same thing happened and the low FET has been shorted also. Now I replaced both FETs and the IC and it seems to somewhat work for now.

I redesigned the PCB a little, with the biggest change being that I moved the low-side mosfet to the top:


I think that by doing that I will have a little bit cleaner current path from the load to the low FET (for the moment when the coil discharges and the high FET is open). But will this actually help?
I know that stuff like this should really be done on a multi-layer board with lots of ground planes, not just 2-layer as I am doing it here, but is this actually the cause of the problem?
What else I did wrong here?

[TimNJ]

The ringing occurs when the converter operates in discontinuous mode (DCM). During the time when you see ringing at the switch-node, the current through the inductor is flat-lined at zero. Under this circumstance, the switch-node will ring at a frequency defined by the buck inductance and the output capacitance(s) of the MOSFET(s). So, it doesn't mean that something is "wrong"...it just means it's operating in DCM.

Loud noise may mean that the control loop is unstable. Take a look at the output ripple. Do you see some sort of modulation of the output ripple on the order of 1-10KHz?

[uer166]

That DCM waveform you have actually looks pretty good. You have a tiny bit of overshoot so it can be better, but it's certainly not bad and would be on-par with a production design. Re: FET failures: what is your actual circuit? How do you set the peak current limit? The controller has a cycle-by-cycle current control with slope compensation so it should be pretty bulletproof as well as not have any audible subharmonic oscillation. Show us the network at the ITH external compensation pin, if anything, your voltage control loop is unstable which is why it's singing.

[T3sl4co1l]

The turn-on ringing is due to the long loop path between capacitors (C13 et al) and transistors.

Are there no stitching vias?  Is that what the "-" actually are?

Try to avoid routing high currents over slots in the opposite layer.  Example: the transistors themselves over the gate drive traces, which cuts that ground return path, making T4 essentially floating in air -- a high inductance path.  This will be evident with an inductive loop probe held over T4 or along the respective traces.  In contrast, T5 will have less.  (They make a tight loop together, so their fields are overlapping; this won't be obvious just from a basic measurement.  It's like a flood light beside a flashlight: both contribute, but the one just seems to modify the shape of the other's field.  In reality, both are independent and superimposed.)

T4 gate drive trace I think can be routed underneath it (top side, between D and S), but there isn't enough room for both.  Better placement might be with T4 and T5 end to end, so the gates come out the same side; place the controller there.  Then ground can be unbroken beneath the transistors, and C13-16 can be placed at either end of the stack (or directly underneath if you don't mind bottom side placement).

Same goes for the current sense traces, which cut up the ground under R23.  C18 doesn't seem to be doing anything, it must be very large indeed to do anything against a shunt resistor.  Some series resistance in the Kelvin sense traces would be preferable.  This is, I think, one of the oddities that LT isn't good about documenting: they prefer as simple an example as possible, even if it results in a poorer product -- see also the lack of gate resistors.

(See https://www.ti.com/lit/ds/symlink/ina240.pdf 9.1.1 for the filtering circuit)

Tim

[Komajster]

@TimNJ @uer166 @T3sl4co1l Thank you all for all this useful information!

Here is how the circuit actually looks like:


And a close-up of the ITH compensation network:


It's mostly based on the Figure 13 from LTC7803's typical applications (datasheet page 33). I just wanted to make a working board and maybe learn something in the process, I was too worried to change anything much   I just increased the input and output capacitance and changed a few components like the diode on the BOOST pin.

Here are some images of the output ripple:



It changes when I put some load on it and this change is audible (more load - higher audible frequency).

Are there no stitching vias?  Is that what the "-" actually are?

Yes, these are the vias, Eagle is just not the best at scaling them and when they are smaller on the board view they look like that.

Try to avoid routing high currents over slots in the opposite layer.  Example: the transistors themselves over the gate drive traces, which cuts that ground return path, making T4 essentially floating in air -- a high inductance path.  This will be evident with an inductive loop probe held over T4 or along the respective traces.  In contrast, T5 will have less.  (They make a tight loop together, so their fields are overlapping; this won't be obvious just from a basic measurement.  It's like a flood light beside a flashlight: both contribute, but the one just seems to modify the shape of the other's field.  In reality, both are independent and superimposed.)

T4 gate drive trace I think can be routed underneath it (top side, between D and S), but there isn't enough room for both.  Better placement might be with T4 and T5 end to end, so the gates come out the same side; place the controller there.  Then ground can be unbroken beneath the transistors, and C13-16 can be placed at either end of the stack (or directly underneath if you don't mind bottom side placement).

Same goes for the current sense traces, which cut up the ground under R23.  C18 doesn't seem to be doing anything, it must be very large indeed to do anything against a shunt resistor.  Some series resistance in the Kelvin sense traces would be preferable.  This is, I think, one of the oddities that LT isn't good about documenting: they prefer as simple an example as possible, even if it results in a poorer product -- see also the lack of gate resistors.

I followed your suggestions and managed to fit both gate drive traces on the top layer, and also I changed how the current sense traces are laid out:


Is this better?
I didn't fully understand what you meant with the "end to end" placement, how it would look like?
Also I will try to think a bit more of those series resistors at the sense traces.

[T3sl4co1l]

Yes, that looks excellent.


Kinda like... well, I decided to hack up the screenshot I guess, enjoy.  Fill in the missing lines and all...

But all of this turned 90 so the inductor is closer to the switching node. (This doesn't save anything in terms of EM, just layout area. Stray inductance in series with an inductor, obviously doesn't matter.)

Tim