It has been a while since my last post, but I have not been idle.

I did a lot of research about different multislope algorithms, and I'm going to mention two here.

While I was waiting for code ( I outsource coding

), I was wondering what kind of topology I could make using just some simple logic I had on hand, and what I came up with was a bounded integrator topology - the integrator waveform oscillates between a set positive and negative limit. This is accomplished using a JK flip-flop (4027) clocked at an arbitrary frequency - the higher the frequency, the less chances of over/undershoot and more resolution. The limit comparators are hooked up to the J and K inputs in a way that turns on the respective ref switch to keep the integrator within bounds. Here is a link to a Falstad simulation:

https://tinyurl.com/y6g6yansSince the slopes are much longer, the number of transitions per clock cycle is considerably lesser than the other topologies I've tried - depending on the clock, the bounded integrator topology has around one transition every 10+ clock cycles, free running has between one transition every clock cycle or less, while the PWM method has exactly two transitions per clock cycle. I assumed that keeping the number of transitions as low as possible would reduce problems due to charge injection. Transitions per clock is a very loose measure of charge injection.

Of course, this method is not without its problems - for one thing, the overall frequency of the integrator ramps changes with changing input up to 50%...initially this didn't seem like a problem to me until I realized that the measurement time would have to vary if I wanted a fixed number of slopes, that is, the counts per clock changes with changing input voltage. One more glaring issue is dielectric absorption, which has plenty of room to manifest itself with slow slopes, which leads to loss of linearity. I was later informed that I had partially re-invented the Solartron 7081 ADC, except that I didn't have that weird square wave injection circuit. I have attached a few images of this bounded integrator that I built on a breadboard.

Since I felt like I was waiting around too much for code, I explored the possibilities of making the PWM algorithm work using discrete logic ICs, and I did end up making something using an 8:1 mux (HC151, for example), a binary counter (HC193) and a D flip-flop (4013):

https://tinyurl.com/y4xps42rMaking the whole thing using logic would be finicky but not difficult - have the microcontroller generate a clock, pulse a pin to start conversion, and read back the output of the counters using PISO shift registers. Of course, just using microcontrollers would be the easiest way out, but I found this little thought experiment fun, and along the way did a lot of thinking about the way results are derived from the PWM topology.

Going the logic way, each PWM cycle takes up (in my case) 8 clock cycles, so it would be possible to get 8 counts per PWM cycle, that is, one count per clock cycle. but since the first and last part of the PWM waveforms cancel each other out (duty cycle is either 12.5% or 87.5%, so the first 12.5% and the last 12.5% cause charges of the same magnitude but opposite polarity in the integrator, so they cancel out) and the main counting happens in the difference in duty cycle extremes. So ultimately it comes down to one count per PWM cycle, or one count every 8 main clock cycles.

With all this boring theory out of the way, I will focus on getting the code up and running and actually post results.

Found this interesting paper:

https://dspace.mit.edu/bitstream/handle/1721.1/84880/868678609-MIT.pdf?sequence=2