Huh, surprised I missed the first thread.
L1 is way, way too small, and only rated 50V. Expect to need much more in general for the line filter.
The waveform indicates saturation due to asymmetrical pulses. I don't know why. Perhaps there's too much ripple into the SG3525.
The ringing is due to leakage inductance, and can be estimated for certain transformer winding geometries. The geometries that aren't so easy to calculate, are also so much worse that they're not useful here, so this is convenient.
First priority is interleaving the secondary half(ves), then interleaving the primary with that. With an output impedance around 5 ohms, the low impedance of layered foil windings will likely be beneficial. You might consider a 16:12 ratio with a transmission line transformer type design, which would need, let's see, a stack of foils
Can also dump the aux winding, move it to the TNY perhaps. This might require a custom wind (though I guess it is anyway, so, eh?), you'll not usually see significant isolation between secondaries of an off-the-shelf inverter transformer. Or could use two smaller ones, primaries in parallel, nothing wrong with that. I mean, the aux winding is kinda neither here nor there, it's rough on C18 but mainly only on startup?
WHOA, IC2 is...
Wait, you've got iso GNDs right beside each other schematically. But they're pinned correctly.
Oh, IC1 is the same way, but at least the iso barrier is drawn there. Sheesh.
Might also help to label 12 and 3.3 by side. Could rename 325VDC_GND to LINK_N say, then 12VDC to LINK12, and 84VDC_GND to just regular GND (or 0 or whatever).
The verbose names are hard to remember:
Fan_speed
B+_sense
Charger_+_sense
Charge_relay_on
Temperature
Fixed_contactor_open
84VDC_Charge_on
Detachable_contactor_open
SC_bank_charge_on
And it's not nice ping-ponging between sheets trying to follow them, the MCU could easily fit on the SG3525 sheet along with the opto (which doesn't connect to ANYTHING on sheet 2!), and more connections can be wired vs. net named.
And, why are there two buffers after the secondary? Oh, there's three pin numbers there, that must be a diode, D1? Ohh, it's the dual diode, yep. Two missing lines makes so much difference.
Anyway, before I get too drawn into schematic layout and style, the stinker here is the lack of current-mode control. This was mentioned in the earlier thread, but I will be much more firm about it.
Simple to add: use the SG3525 error amp to set PWM based on feedback current, sensed with an isolated (Hall effect) sensor on L2. At this current level, HE is perfectly acceptable; a 15 or 20A range device will do, I suppose.
The SG3525 is then a transconductance amplifier, taking in a reference voltage (from the MCU, I assume that's a DAC output) and putting out a current. The MCU then runs a PID loop to maintain output voltage.
The inner loop is designed so that, under absolutely any condition -- startup, short circuit, open, whatever -- the output current is limited, and safe with respect to inverter capacity.
This avoids so many stupid nuisance failures of the switches, and makes limiting output current almost trivial (fully trivial, if the current limit needn't be variable). Current mode control is an absolute priority.
Can even go to the length of adding a fault latch and desat protection (disables output if a transistor shows significant voltage drop while conducting), though I wouldn't find that a priority at this power level. I do recommend it for industrial scale (3kW+) supplies. So, it's close, could certainly give it a try, but it's also not too terribly annoying to fix, if/when it blows up.
You do need a better analog isolator. IC1 will not do. Its CTR and offset vary wildly with temperature and age (worse than +/-50%). A more likely option here is a PWMDAC, using PWM straight from the MCU, a digital isolator, and an RC (or better) filter. A 5V-compatible isolator can run directly from Vref, no worries.
Do check your compensation network. C33 is completely out of place. Did you mean to name CC_CV_emitter as INV_in? As is, I think C35-R35 dead-ends. Who knows, I can't follow net labels everywhere, but I don't see another search result at least. Also as is, the opto is probably a constant current, but it will have significant AC impedance, affecting compensation itself. Probably better to use it as a reference (to NONINV_in?). And also as shown, gain is very high (assuming the above interpretation is the correct intent), then R35 into R47 is massive gain, exacerbating the offset and gain errors of IC1. Or if it was intended to be sensing output voltage, then R35 should be in series with C35 to get good output regulation; but anyway, that seems to be the MCU's responsibility, so it shouldn't have capacitors at all (or large ones, at least), and a software PID loop or whatever should be serving that purpose instead.
Mind that, if you do change to PWMDAC, the PWM filter will likely be the dominant pole in the system, much slower than the modulator itself (i.e., 3525 input setpoint to L2 output current). For a charger, this is irrelevant, regulation only needs to be met at quite low frequencies (fractional Hz?), and anything higher is gravy. If you intend to also use this as a general purpose supply, you may find it attractive to add an SPI or S-D DAC instead. Or isolate the gate signals, and move the 3525 to the secondary side.
Or drive it entirely by the MCU itself (full digital), but I certainly wouldn't recommend that as a starting project! At least, not without more protective logic (fast watchdog timer and shoot-thru fault, optional desat fault).
Tim
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