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| 1.5 to 3 MHz frequency doubler circuit |
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| Wolfgang:
--- Quote from: Gandalf_Sr on December 27, 2018, 02:00:04 pm ---I have a design where a Cypress BLE module feeds I2S audio data to a TAS5755M TI Amplifier. The problem is that the Amp needs an extra clock signal called MCLK of 3.072 MHz and it needs to be a doubled, synched multiple the I2S SCLK signal of 1.536 MHz. I built a circuit like this... https://www.maximintegrated.com/en/app-notes/index.mvp/id/3327 But there's a lot of jitter and variations on the mark-space ratio on the output so it's very unreliable and only works occasionally. I thought it would be simple to build a PLL circuit set up as a doubler with 1.536MHz in and 3.072 MHz out but all the ICs I've looked at have a minimum output frequency that's too low (I looked at the 74HC4046a and the PT7C4511). Can anyone here suggest an IC or circuit that will meet my needs? My operating voltage is 3.3V. Thanks in advance. --- End quote --- The jitter free solution is a balanced doubler, like here (you need to scroll down a bit): https://electronicprojectsforfun.wordpress.com/a-clean-23cm-signal-source/ The advantage of a balanced doubler is best signal quality with very low jitter and cancellation of harmonics. You need to adapt the circuit to 3.3V. If you need a digital output, a Schmitt trigger could be added at the output. |
| ogden:
--- Quote from: Wolfgang on December 28, 2018, 02:58:13 pm ---The jitter free solution is a balanced doubler, like here (you need to scroll down a bit): https://wordpress.com/view/electronicprojectsforfun.wordpress.com The advantage of a balanced doubler is best signal quality with very low jitter and cancellation of harmonics. You need to adapt the circuit to 3.3V. If you need a digital output, a Schmitt trigger could be added at the output. --- End quote --- URL does not look right. |
| Wolfgang:
Thanks, I fixed it. |
| edavid:
--- Quote from: Gandalf_Sr on December 28, 2018, 09:34:29 am ---I'm discarding the transformer rectifier option as too expensive and large. --- End quote --- A T37-2 core, a few inches of wire, and a couple of diodes are expensive and large? :-// |
| SiliconWizard:
--- Quote from: Gandalf_Sr on December 28, 2018, 09:34:29 am ---I have played with the R1 C1 values but, as has been predicted, the results can drift or be inconsistent. --- End quote --- To get a much more precise and stable delay, you could also use a digital delay line instead of this RC circuit. Then the XOR gate doesn't need schmitt trigger inputs either. Examples are DS1100L or DS1110L. https://www.maximintegrated.com/en/products/digital/clock-generation-distribution/DS1100L.html Not quite cheap but for a few bucks more (around $5 in small quantities), this will be a whole lot better. |
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