| Electronics > Projects, Designs, and Technical Stuff |
| 1.5 to 3 MHz frequency doubler circuit |
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| Wolfgang:
If you need to phase align with the original signal you can use a phase shifter before digitizing. Another idea is a PLL, which does the same with more jitter. |
| Buriedcode:
According to the datasheet, the amplifier can use its internal oscillator, which I assume is phase locked to the SCLK input: --- Quote ---The clock section uses MCLK or the internal oscillator clock (when MCLK is unstable, out of range, or absent) to produce the internal clock (DCLK) running at 512 times the PWM switching frequency. --- End quote --- With an SCLK of 1.536MHz you either have a sample rate of 24kHz with 64 SCLK periods per frame, or more likely 48kHz with only 32 sclk's per frame. It seems the amplifier can accept this, so I'm not sure you really need a frequency doubler. It *should* have its own internal 24.576MHz clock running from a PLL. The amplifier looks quite impressive, I might pick one up to play with - has a number of advanced features! |
| dmendesf:
Look for 74hct9046. It's a newer version of 4046 with a few bugs ironed out. I've used it to generate > 15MHz signals, although the design equations don't work very well at this frequency and some trial and error is mandatory. |
| edavid:
--- Quote from: dmendesf on December 29, 2018, 09:34:01 pm ---Look for 74hct9046. It's a newer version of 4046 with a few bugs ironed out. I've used it to generate > 15MHz signals, although the design equations don't work very well at this frequency and some trial and error is mandatory. --- End quote --- OP is running his circuit at 3.3V, so the 74HCT9046 would not work. (Also, the improvements don't matter for his application.) |
| langwadt:
--- Quote from: Buriedcode on December 29, 2018, 04:58:54 pm ---According to the datasheet, the amplifier can use its internal oscillator, which I assume is phase locked to the SCLK input: --- Quote ---The clock section uses MCLK or the internal oscillator clock (when MCLK is unstable, out of range, or absent) to produce the internal clock (DCLK) running at 512 times the PWM switching frequency. --- End quote --- With an SCLK of 1.536MHz you either have a sample rate of 24kHz with 64 SCLK periods per frame, or more likely 48kHz with only 32 sclk's per frame. It seems the amplifier can accept this, so I'm not sure you really need a frequency doubler. It *should* have its own internal 24.576MHz clock running from a PLL. --- End quote --- I looked at the datasheet and is clear as mud on how the it should be clocked, but afaict it will mute the output if it isn't clocked just right |
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